| /bsp/renesas/ra6e2-fpb/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/ |
| A D | armv7m_cachel1.h | 65 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
98 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
151 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
213 SCB->DCCIMVAC = (uint32_t)&locals.sets; in SCB_DisableDCache()
214 SCB->DCCIMVAC = (uint32_t)&locals.ways; in SCB_DisableDCache()
215 SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; in SCB_DisableDCache()
217 SCB->DCCIMVAC = (uint32_t)&locals; in SCB_DisableDCache()
223 locals.ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
257 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
292 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra4e2-eco/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/ |
| A D | armv7m_cachel1.h | 65 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
98 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
152 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
214 SCB->DCCIMVAC = (uint32_t)&locals.sets; in SCB_DisableDCache()
215 SCB->DCCIMVAC = (uint32_t)&locals.ways; in SCB_DisableDCache()
216 SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; in SCB_DisableDCache()
218 SCB->DCCIMVAC = (uint32_t)&locals; in SCB_DisableDCache()
224 locals.ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
258 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
293 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/at32/libraries/CMSIS/include/ |
| A D | cachel1_armv7.h | 67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
215 SCB->DCCIMVAC = (uint32_t)&locals.sets; in SCB_DisableDCache()
216 SCB->DCCIMVAC = (uint32_t)&locals.ways; in SCB_DisableDCache()
217 SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; in SCB_DisableDCache()
219 SCB->DCCIMVAC = (uint32_t)&locals; in SCB_DisableDCache()
225 locals.ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
259 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
294 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/airm2m/air32f103/libraries/CMSIS/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/tae32f5300/Libraries/CMSIS/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra6m4-iot/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra6m3-hmi-board/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra4m2-eco/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/renesas/ra8d1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
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| /bsp/rockchip/common/rk_hal/lib/hal/src/pm/ |
| A D | hal_pm_cpu.c | 225 scbSave.ICSR = SCB->ICSR; in HAL_SCB_SuspendSave()
227 scbSave.SCR = SCB->SCR; in HAL_SCB_SuspendSave()
232 scbSave.CFSR = SCB->CFSR; in HAL_SCB_SuspendSave()
233 scbSave.DFSR = SCB->DFSR; in HAL_SCB_SuspendSave()
235 scbSave.BFAR = SCB->BFAR; in HAL_SCB_SuspendSave()
236 scbSave.AFSR = SCB->AFSR; in HAL_SCB_SuspendSave()
247 SCB->ICSR = scbSave.ICSR; in HAL_SCB_ResumeRestore()
249 SCB->SCR = scbSave.SCR; in HAL_SCB_ResumeRestore()
254 SCB->CFSR = scbSave.CFSR; in HAL_SCB_ResumeRestore()
255 SCB->DFSR = scbSave.DFSR; in HAL_SCB_ResumeRestore()
[all …]
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| /bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ |
| A D | lpm.c | 108 …SCB->SCR = pstcConfig->enSEVONPEND ? (SCB->SCR | SCB_SCR_SEVONPEND_Msk) : (SCB->SCR & ~SCB_SCR… in Lpm_Config()
109 …SCB->SCR = pstcConfig->enSLEEPDEEP ? (SCB->SCR | SCB_SCR_SLEEPDEEP_Msk) : (SCB->SCR & ~SCB_SCR… in Lpm_Config()
110 …SCB->SCR = pstcConfig->enSLEEPONEXIT ? (SCB->SCR | SCB_SCR_SLEEPONEXIT_Msk) : (SCB->SCR & ~SCB_SCR… in Lpm_Config()
|
| /bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/ |
| A D | stm32l1xx_ll_cortex.h | 313 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
324 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
337 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
348 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
360 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
372 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
395 SET_BIT(SCB->SHCSR, Fault); in LL_HANDLER_EnableFault()
410 CLEAR_BIT(SCB->SHCSR, Fault); in LL_HANDLER_DisableFault()
438 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); in LL_CPUID_GetVariant()
458 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); in LL_CPUID_GetParNo()
[all …]
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| /bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32f20x_pwr.c | 128 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTOPMode()
139 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); in PWR_EnterSTOPMode()
152 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTANDBYMode()
220 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTOPMode_RAM()
231 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); in PWR_EnterSTOPMode_RAM()
259 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTOPMode_RAM_LV()
270 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); in PWR_EnterSTOPMode_RAM_LV()
293 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTANDBYMode_RAM()
322 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTANDBYMode_RAM_LV()
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| /bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/ |
| A D | stm32l1xx_hal_pwr.c | 456 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode()
502 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode()
518 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode()
538 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode()
560 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
573 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
586 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
599 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
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| /bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/ |
| A D | apm32f0xx_misc.c | 106 SCB->SCR |= lowPowerMode; in NVIC_EnableSystemLowPower()
122 SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode); in NVIC_DisableSystemLowPower()
156 SCB->SCR &= (uint32_t)(~(uint32_t)NVIC_LOWPOER_SLEEPDEEP); in PMU_EnterWaitMode()
169 SCB->SCR |= NVIC_LOWPOER_SLEEPDEEP; in PMU_EnterHaltModeWFI()
183 SCB->SCR |= NVIC_LOWPOER_SLEEPDEEP; in PMU_EnterHaltModeWFE()
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