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Searched refs:SCB_CPUID_ARCHITECTURE_Msk (Results 1 – 25 of 627) sorted by relevance

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/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_cortex.h448 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); in LL_CPUID_GetConstant()
/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/
A Dcore_cm0.h313 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/efm32/Libraries/CMSIS/Include/
A Dcore_cm0.h311 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
A Dcore_cm0plus.h326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/CME_M7/CMSIS/CMSIS/Include/
A Dcore_cm0.h326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
A Dcore_sc000.h334 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
A Dcore_cm0plus.h341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/
A Dcore_cm0.h326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
A Dcore_sc000.h334 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/mm32l07x/Libraries/CMSIS/CORE/
A Dcore_cm0.h311 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/mm32l3xx/Libraries/CMSIS/KEIL_CORE/
A Dcore_cm0.h311 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/Core/
A Dcore_cm0.h326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/nxp/lpc/lpc43xx/Libraries/CMSIS/Include/
A Dcore_cm0.h326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/
A Dcore_cm0.h301 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/xplorer4330/Libraries/CMSIS/Include/
A Dcore_cm0.h326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/essemi/es32f0654/libraries/CMSIS/Include/
A Dcore_cm0.h312 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/
A Dcore_cm0.h355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
A Dcore_cm0plus.h370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dcore_cm0.h346 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
A Dcore_cm0plus.h361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/samd21/sam_d2x_asflib/CMSIS/Include/
A Dcore_cm0.h355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/mm32l07x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0.h355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/mm32l3xx/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0.h355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0.h345 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro
/bsp/wch/arm/ch579m/libraries/CMSIS/Include/
A Dcore_cm0.h355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB … macro

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