| /bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/ |
| A D | core_cm0.h | 318 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
319 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/efm32/Libraries/CMSIS/Include/ |
| A D | core_cm0.h | 316 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
317 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| A D | core_cm0plus.h | 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/CME_M7/CMSIS/CMSIS/Include/ |
| A D | core_cm0.h | 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| A D | core_sc000.h | 339 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
340 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| A D | core_cm0plus.h | 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/ |
| A D | core_cm0.h | 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| A D | core_sc000.h | 339 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
340 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| A D | core_cm0plus.h | 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/mm32l07x/Libraries/CMSIS/CORE/ |
| A D | core_cm0.h | 316 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
317 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/mm32l3xx/Libraries/CMSIS/KEIL_CORE/ |
| A D | core_cm0.h | 316 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
317 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/Core/ |
| A D | core_cm0.h | 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/nxp/lpc/lpc43xx/Libraries/CMSIS/Include/ |
| A D | core_cm0.h | 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/ |
| A D | core_cm0.h | 306 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
307 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/xplorer4330/Libraries/CMSIS/Include/ |
| A D | core_cm0.h | 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/essemi/es32f0654/libraries/CMSIS/Include/ |
| A D | core_cm0.h | 317 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
318 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/ |
| A D | core_cm0.h | 360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| A D | core_cm0plus.h | 375 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
376 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ |
| A D | core_cm0.h | 351 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
352 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| A D | core_cm0plus.h | 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/samd21/sam_d2x_asflib/CMSIS/Include/ |
| A D | core_cm0.h | 360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/mm32l07x/Libraries/CMSIS/IAR_CORE/ |
| A D | core_cm0.h | 360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/mm32l3xx/Libraries/CMSIS/IAR_CORE/ |
| A D | core_cm0.h | 360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/ |
| A D | core_cm0.h | 350 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
351 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
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| /bsp/wch/arm/ch579m/libraries/CMSIS/Include/ |
| A D | core_cm0.h | 360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
|