SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK (reference) in projects: bsp

Searched refs:SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK (Results 1 – 6 of 6) sorted by relevance

/bsp/renesas/rzn2l_etherkit/rzn_gen/
A D	hal_data.c	`45 .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,`
/bsp/renesas/rzn2l_rsk/rzn_gen/
A D	hal_data.c	`45 .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,`
/bsp/renesas/rzt2m_rsk/rzt_gen/
A D	hal_data.c	`45 .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,`
/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/
A D	r_sci_uart.h	`144 SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0, enumerator`
/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/
A D	r_sci_uart.h	`144 SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0, enumerator`
/bsp/renesas/rzn2l_etherkit/rzn/fsp/inc/instances/
A D	r_sci_uart.h	`144 SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0, enumerator`

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