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Searched refs:SDADC_SYNCBUSY_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/microchip/samc21/bsp/hri/
A Dhri_sdadc_c21.h467 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_set_CTRLA_RUNSTDBY_bit()
487 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_write_CTRLA_RUNSTDBY_bit()
495 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_clear_CTRLA_RUNSTDBY_bit()
503 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_toggle_CTRLA_RUNSTDBY_bit()
511 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_set_CTRLA_ONDEMAND_bit()
531 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_write_CTRLA_ONDEMAND_bit()
539 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_clear_CTRLA_ONDEMAND_bit()
547 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_toggle_CTRLA_ONDEMAND_bit()
1247 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_set_INPUTCTRL_MUXSEL_bf()
1268 hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); in hri_sdadc_write_INPUTCTRL_MUXSEL_bf()
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/bsp/microchip/samc21/bsp/samc21/include/component/
A Dsdadc.h485 #define SDADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (SDADC_SYNCBUSY) MASK Register */ macro

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