Searched refs:SDIF_CLK_CTRL (Results 1 – 2 of 2) sorted by relevance
| /bsp/cvitek/drivers/ |
| A D | drv_sdhci.c | 80 mmio_write_16(BASE + SDIF_CLK_CTRL, in sdhci_set_card_clock()
82 mmio_write_16(BASE + SDIF_CLK_CTRL, in sdhci_set_card_clock()
85 mmio_write_16(BASE + SDIF_CLK_CTRL, in sdhci_set_card_clock()
130 …mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_32(BASE + SDIF_CLK_CTRL) & ~(0x1<<2)); // stop SD cl… in SDIF_ChangeCardClock()
155 …mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_16(BASE + SDIF_CLK_CTRL) & ~(0x1<<2)); // stop SD cl… in SDIF_ChangeCardClock()
158 …mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_16(BASE + SDIF_CLK_CTRL) & ~0x8); // disable PLL_EN… in SDIF_ChangeCardClock()
169 …mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_16(BASE + SDIF_CLK_CTRL) & ~(0x1 << 5)); // CLK_GEN_… in SDIF_ChangeCardClock()
172 …mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_16(BASE + SDIF_CLK_CTRL) | 0xc); // enable PLL_ENAB… in SDIF_ChangeCardClock()
599 …mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_32(BASE + SDIF_CLK_CTRL) | (0x1<<2)); // stop SD clo… in sdhci_enable_card_clock()
739 mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_16(BASE + SDIF_CLK_CTRL) & ~(0x1 << 5)); in sdhci_init()
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| /bsp/cvitek/drivers/libraries/sdif/ |
| A D | dw_sdmmc.h | 127 #define SDIF_CLK_CTRL 0x2C macro
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