Searched refs:SDIF_HOST_CONTROL2 (Results 1 – 2 of 2) sorted by relevance
74 if (mmio_read_16(BASE + SDIF_HOST_CONTROL2) & 1<<15) in sdhci_set_card_clock()160 if (mmio_read_16(BASE + SDIF_HOST_CONTROL2) & 1<<15) in SDIF_ChangeCardClock()164 …mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) & ~0x7); // clr U… in SDIF_ChangeCardClock()557 ctrl_2 = mmio_read_16(BASE + SDIF_HOST_CONTROL2); in sdhci_set_bus_width()560 mmio_write_16(BASE + SDIF_HOST_CONTROL2, ctrl_2); in sdhci_set_bus_width()738 mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) | 1<<11); in sdhci_init()740 …mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) | SDIF_HOST_VER4_… in sdhci_init()742 mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) | 0x1<<13); in sdhci_init()746 …mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) | (0x1<<14)); // … in sdhci_init()751 …mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) & ~(0x1<<8)); // … in sdhci_init()[all …]
142 #define SDIF_HOST_CONTROL2 0x3E macro
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