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Searched refs:SDIO_CR2_SDCLKDIV_Pos (Results 1 – 6 of 6) sorted by relevance

/bsp/synwit/libraries/SWM341_CSL/SWM341_StdPeriph_Driver/
A DSWM341_sdio.c57 (calcSDCLKDiv(100000) << SDIO_CR2_SDCLKDIV_Pos) | in SDIO_Init()
112 (calcSDCLKDiv(freq) << SDIO_CR2_SDCLKDIV_Pos); //初始化完成，SDCLK切换到高速 in SDIO_Init()
641 (calcSDCLKDiv(freq) << SDIO_CR2_SDCLKDIV_Pos) | in SDIO_IO_Init()
/bsp/synwit/libraries/SWM320_CSL/SWM320_StdPeriph_Driver/
A DSWM320_sdio.c58 (calcSDCLKDiv(100000) << SDIO_CR2_SDCLKDIV_Pos) | in SDIO_Init()
113 (calcSDCLKDiv(freq) << SDIO_CR2_SDCLKDIV_Pos); //初始化完成，SDCLK切换到高速 in SDIO_Init()
/bsp/synwit/libraries/SWM320_drivers/
A Ddrv_sdio.c449 (clkcr << SDIO_CR2_SDCLKDIV_Pos) | in swm_sdio_set_iocfg()
/bsp/synwit/libraries/SWM341_drivers/
A Ddrv_sdio.c449 (clkcr << SDIO_CR2_SDCLKDIV_Pos) | in swm_sdio_set_iocfg()
/bsp/synwit/libraries/SWM320_CSL/CMSIS/DeviceSupport/
A DSWM320.h2556 #define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 不分频 0x01 2分频 0x02 4分频… macro
2557 #define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos)
/bsp/synwit/libraries/SWM341_CSL/CMSIS/DeviceSupport/
A DSWM341.h2354 #define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 不分频 0x01 2分频 0x02 4分频… macro
2355 #define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos)

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