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Searched refs:SDxCON (Results 1 – 3 of 3) sorted by relevance

/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/
A Dab32vg1_hal_sd.c36 sdiox[SDxCON] = 0; in sdio_init()
39 sdiox[SDxCON] |= BIT(0); /* SD control enable */ in sdio_init()
42 sdiox[SDxCON] |= BIT(3); /* Keep clock output */ in sdio_init()
44 sdiox[SDxCON] &= ~BIT(3); /* Keep clock output */ in sdio_init()
46 sdiox[SDxCON] |= BIT(5); /* Data interrupt enable */ in sdio_init()
60 if (sdiox[SDxCON] & BIT(12)) { in sdio_check_finish()
76 return !(sdiox[SDxCON] & BIT(15)); in sdio_check_rsp()
/bsp/bluetrum/libraries/hal_drivers/
A Ddrv_sdio.c312 LOG_E("SDxCON=0x%X SDxCMD=0x%X\n", hw_sdio[SDxCON], hw_sdio[SDxCMD]); in rthw_sdio_send_command()
317 if (((hw_sdio[SDxCON] & HW_SDIO_CON_CRCS) >> 17) != 2) { in rthw_sdio_send_command()
430 hw_sdio[SDxCON] &= ~BIT(0); in rthw_sdio_iocfg()
434 hw_sdio[SDxCON] = 0; in rthw_sdio_iocfg()
437 hw_sdio[SDxCON] |= BIT(0); /* SD control enable */ in rthw_sdio_iocfg()
439 hw_sdio[SDxCON] |= BIT(3); /* Keep clock output */ in rthw_sdio_iocfg()
440 hw_sdio[SDxCON] |= BIT(4); in rthw_sdio_iocfg()
441 hw_sdio[SDxCON] |= BIT(5); /* Data interrupt enable */ in rthw_sdio_iocfg()
447 hw_sdio[SDxCON] &= ~BIT(3); in rthw_sdio_iocfg()
505 rt_uint32_t intstatus = hw_sdio[SDxCON]; in rthw_sdio_irq_process()
/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/
A Dab32vg1_ll_sdio.h26 SDxCON = 0, /* [20]:BUSY [19:17]:CRCS [16]:DCRCE [15]:NRPS [1]:Data bus width [0]:SD enable */ enumerator

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