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Searched refs:SERCOM2_GCLK_ID_CORE (Results 1 – 10 of 10) sorted by relevance

/bsp/microchip/samd51-seeed-wio-terminal/bsp/
A Ddriver_init.c29 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCH… in TARGET_IO_CLOCK_init()
/bsp/microchip/saml10/bsp/
A Ddriver_init.c95 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCH… in TARGET_IO_CLOCK_init()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/
A Dsercom2.h130 #define SERCOM2_GCLK_ID_CORE 15 macro
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/
A Dsercom2.h139 #define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core macro
/bsp/microchip/samc21/bsp/samc21/include/instance/
A Dsercom2.h127 #define SERCOM2_GCLK_ID_CORE 21 macro
/bsp/microchip/saml10/bsp/include/instance/
A Dsercom2.h135 #define SERCOM2_GCLK_ID_CORE 13 macro
/bsp/microchip/same54/bsp/include/instance/
A Dsercom2.h145 #define SERCOM2_GCLK_ID_CORE 23 macro
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/instance/
A Dsercom2.h145 #define SERCOM2_GCLK_ID_CORE 23 macro
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/instance/
A Dsercom2.h145 #define SERCOM2_GCLK_ID_CORE 23 macro
/bsp/microchip/same54/bsp/
A Ddriver_init.c72 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCH… in TARGET_IO_CLOCK_init()

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