1 /* 2 * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_ 18 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_ 19 #include "core-v-mcu-properties.h" 20 21 /* Events offsets. */ 22 #define UDMA_EVENT_OFFSET_RX (0U) 23 #define UDMA_EVENT_OFFSET_TX (1U) 24 #define EVENT_UART_RX (2U) 25 #define EVENT_UART_ERR (3U) 26 27 #define UDMA_EVENT_OFFSET_SPI_CMD (2) 28 #define UDMA_EVENT_OFFSET_SPI_EOT (3) 29 30 /* Number of events per peripheral. */ 31 #define UDMA_CHANNEL_NB_EVENTS_LOG2 (2) 32 #define UDMA_CHANNEL_NB_EVENTS (1 << UDMA_CHANNEL_NB_EVENTS_LOG2) 33 34 /* Number of SW events. */ 35 #define NB_SW_EVENTS (8) 36 37 /*! @brief FC events (aka IRQ lines)*/ 38 #define FC_EVENT_SW(id) (id & (NB_SW_EVENTS - 1)) 39 #define FC_EVENT_DMA_EVT (8) 40 #define FC_EVENT_DMA (9) 41 #define FC_EVENT_TIMER0 (10) /* Timer low. */ 42 #define SYSTICK_IRQN FC_EVENT_TIMER0 43 #define FC_EVENT_TIMER1 (11) /* Timer high. */ 44 /* #define FC_EVENT_EU_HWCE (12) */ 45 46 /* 47 * SoC event unit events: Many events get implicitely muxed into this interrupt. 48 * A user that gets such an interrupt has to check the event unit's registers to 49 * see what happened 50 */ 51 #define FC_EVENT_SOC_EVENT (27) 52 /* #define FC_EVENT_MPU_ERROR (28) */ 53 /* 54 * Event queue error: If we don't process event unit events quickly enough 55 * internal fifos can overflow and we get this error interrupt 56 */ 57 #define FC_EVENT_FC_QUEUE_ERROR (29) 58 #define FC_EVENT_HP0 runn (30) 59 #define FC_EVENT_HP1 (31) 60 61 /*! @name SoC events */ 62 /*! @brief Number of FC_Events. */ 63 #define SOC_EU_NB_FC_EVENTS (168) 64 65 /*! @brief UDMA events */ 66 /* SPIM */ 67 #define SOC_EVENT_UDMA_SPIM_RX(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) 68 #define SOC_EVENT_UDMA_SPIM_TX(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) 69 #define SOC_EVENT_UDMA_SPIM_CMD(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_CMD) 70 #define SOC_EVENT_UDMA_SPIM_EOT(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_EOT) 71 /* HYPER */ 72 /* #define SOC_EVENT_UDMA_HYPER_RX(id) ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */ 73 /* #define SOC_EVENT_UDMA_HYPER_TX(id) ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */ 74 /* UART */ 75 #define SOC_EVENT_UDMA_UART_RX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) 76 #define SOC_EVENT_UDMA_UART_TX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) 77 #define SOC_EVENT_UART_RX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_RX) 78 #define SOC_EVENT_UART_ERR(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_ERR) 79 /* I2C */ 80 #define SOC_EVENT_UDMA_I2C_RX(id) ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) 81 #define SOC_EVENT_UDMA_I2C_TX(id) ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) 82 /* DMACPY */ 83 /* #define SOC_EVENT_UDMA_DMACPY_RX(id) ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */ 84 /* #define SOC_EVENT_UDMA_DMACPY_TX(id) ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */ 85 /* I2S */ 86 #define SOC_EVENT_UDMA_I2S_RX(id) ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) 87 #define SOC_EVENT_UDMA_I2S_TX(id) ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) 88 /* CPI */ 89 #define SOC_EVENT_UDMA_CAM_RX(id) ((UDMA_CAM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) 90 91 /* UDMA EOT & error events. */ 92 //#define SOC_EVENT_UDMA_I2C_ERROR(id) (26 + id) 93 94 /*! @brief PMU events, no pmu*/ 95 /* #define SOC_EVENT_PMU_CLUSTER_POWER (31) */ 96 /* #define SOC_EVENT_PMU_CLUSTER_CG (35) */ 97 /* #define SOC_EVENT_PMU_DLC_BRIDGE_PICL (36) */ 98 /* #define SOC_EVENT_PMU_DLC_BRIDGE_SCU (37) */ 99 /* #define SOC_EVENT_PWM(id) (38 + id) */ 100 #define SOC_EVENT_GPIO (139) 101 #define SOC_EVENT_HWPE0 (140) 102 #define SOC_EVENT_HWPE1 (141) 103 /* #define SOC_EVENT_RTC_APB (43) */ 104 /* #define SOC_EVENT_RTC (44) */ 105 106 #define SOC_EVENT_SW(id) (160 + (id & (NB_SW_EVENTS - 1))) 107 #define SOC_EVENT_REF32K_CLK_RISE (168) 108 109 /* @brief Cluster events */ 110 #define CL_EVENT_SW(id) (id & (NB_SW_EVENTS - 1)) 111 #define CL_EVENT_DMA0 (8) 112 #define CL_EVENT_DMA1 (9) 113 #define CL_EVENT_TIMER0_LO (10) 114 #define CL_EVENT_TIMER0_HI (11) 115 #define CL_EVENT_ACC0 (12) 116 #define CL_EVENT_ACC1 (13) 117 #define CL_EVENT_ACC2 (14) 118 #define CL_EVENT_ACC3 (15) 119 #define CL_EVENT_BAR (16) 120 #define CL_EVENT_MUTEX (17) 121 #define CL_EVENT_DISPATCH (18) 122 /* #define CL_EVENT_CLUSTER0 (22) */ 123 /* #define CL_EVENT_CLUSTER1 (23) */ 124 #define CL_EVENT_SOC_EVT (30) /* adapted */ 125 126 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_ */ 127