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123

/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/
A Dn32l40x_flash.h288 #define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE)) argument
300 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
312 #define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST)) argument
324 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) argument
336 #define IS_OB_PD_SOURCE(SOURCE) (((SOURCE) == OB_PD_NORST) || ((SOURCE) == OB_PD_RST)) argument
348 #define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE)) argument
360 #define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR)) argument
372 #define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR)) argument
384 #define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT… argument
402 #define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \ argument
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/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/
A Dn32l43x_flash.h288 #define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE)) argument
300 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
312 #define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST)) argument
324 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) argument
336 #define IS_OB_PD_SOURCE(SOURCE) (((SOURCE) == OB_PD_NORST) || ((SOURCE) == OB_PD_RST)) argument
348 #define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE)) argument
360 #define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR)) argument
372 #define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR)) argument
384 #define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT… argument
402 #define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \ argument
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A Dn32l43x_rcc.h132 #define IS_RCC_PLL_SRC(SOURCE) … argument
133 …(((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2) …
134 || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2))
203 #define IS_RCC_SYSCLK_SRC(SOURCE) … argument
204 …(((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI) …
205 || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK))
295 …(((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) …
296 || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3))
559 …(((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_…
560 || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32))
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/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/
A Dn32g43x_flash.h288 #define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE)) argument
300 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
312 #define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST)) argument
324 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) argument
336 #define IS_OB_PD_SOURCE(SOURCE) (((SOURCE) == OB_PD_NORST) || ((SOURCE) == OB_PD_RST)) argument
348 #define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE)) argument
360 #define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR)) argument
372 #define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR)) argument
384 #define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT… argument
402 #define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \ argument
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/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/
A Dft32f0xx_rcc.h75 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ argument
76 ((SOURCE) == RCC_PLLSource_HSI48) || \
77 ((SOURCE) == RCC_PLLSource_HSI) || \
79 ((SOURCE) == RCC_PLLSource_PREDIV1))
156 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ argument
334 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ argument
446 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSourc… argument
447 … ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \
448 … ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
449 … ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \
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A Dft32f0xx_flash.h180 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
192 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) argument
204 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) argument
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/inc/
A Dhk32f0xx_rcc.h71 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ argument
72 ((SOURCE) == RCC_PLLSource_HSI) || \
73 ((SOURCE) == RCC_PLLSource_HSE) || \
74 ((SOURCE) == RCC_PLLSource_PREDIV1))
150 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ argument
152 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
313 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ argument
414 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSourc… argument
415 … ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \
416 … ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
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A Dhk32f0xx_flash.h145 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
157 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) argument
169 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) argument
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x_rcc.h64 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ argument
65 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
66 ((SOURCE) == RCC_PLLSource_HSE_Div2))
132 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ argument
133 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
134 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
211 …#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || ((SOURCE) == … argument
212 … ((SOURCE) == RCC_USBCLKSource_PLLCLK_2Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2) || \
213 … ((SOURCE) == RCC_USBCLKSource_PLLCLK_3Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div3) || \
214 … ((SOURCE) == RCC_USBCLKSource_PLLCLK_4Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div4))
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A Dair32f10x_flash.h215 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
227 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) argument
239 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) argument
A Dair32f10x_tim.h684 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000… argument
741 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ argument
810 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x00… argument
824 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ argument
879 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ argument
880 ((SOURCE) == TIM_TRGOSource_Enable) || \
881 ((SOURCE) == TIM_TRGOSource_Update) || \
882 ((SOURCE) == TIM_TRGOSource_OC1) || \
883 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
884 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
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/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/inc/
A DHAL_rcc.h79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ argument
80 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
81 ((SOURCE) == RCC_PLLSource_HSE_Div2))
95 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ argument
96 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
97 ((SOURCE) == RCC_SYSCLKSource_PLLCLK||(SOURCE) == RCC_SYSCLKSource_LSI))
201 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \ argument
202 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div3)|| \
203 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div4))
A DHAL_flash.h193 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
205 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) argument
217 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) argument
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/inc/
A DHAL_rcc.h79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ argument
80 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
81 ((SOURCE) == RCC_PLLSource_HSE_Div2))
94 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ argument
95 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
96 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
202 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \ argument
203 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2))
242 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ argument
243 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
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A DHAL_flash.h193 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
205 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) argument
217 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) argument
A DHAL_tim.h557 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000… argument
560 (((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
562 (((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
564 (((SOURCE) & (uint16_t)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
620 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ argument
689 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x00… argument
707 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ argument
708 ((SOURCE) == TIM_UpdateSource_Regular))
762 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ argument
763 ((SOURCE) == TIM_TRGOSource_Enable) || \
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/bsp/tkm32F499/Libraries/Hal_lib/inc/
A DHAL_rcc.h79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ argument
80 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
81 ((SOURCE) == RCC_PLLSource_HSE_Div2))
94 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ argument
95 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
96 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
214 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ argument
215 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
254 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ argument
255 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
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A DHAL_flash.h193 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
205 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) argument
217 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) argument
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/
A DHAL_rcc.h79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ argument
80 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
81 ((SOURCE) == RCC_PLLSource_HSE_Div2))
94 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ argument
95 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
96 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
202 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \ argument
203 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2))
242 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ argument
243 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
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A DHAL_flash.h193 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
205 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) argument
217 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) argument
A DHAL_tim.h557 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000… argument
560 (((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
562 (((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
564 (((SOURCE) & (uint16_t)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
620 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ argument
689 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x00… argument
707 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ argument
762 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ argument
763 ((SOURCE) == TIM_TRGOSource_Enable) || \
765 ((SOURCE) == TIM_TRGOSource_OC1) || \
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/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/
A Dn32g45x_flash.h254 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
266 #define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST)) argument
278 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) argument
/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/
A Dn32g4fr_flash.h254 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
266 #define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST)) argument
278 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) argument
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/
A Dn32wb452_flash.h254 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
266 #define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST)) argument
278 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) argument
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/
A Dn32g45x_flash.h254 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) argument
266 #define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST)) argument
278 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) argument

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