Searched refs:SPI_IMR (Results 1 – 5 of 5) sorted by relevance
69 return (((Spi *)hw)->SPI_IMR & SPI_IMR_RDRF) >> SPI_IMR_RDRF_Pos; in hri_spi_get_IMR_RDRF_bit()93 return (((Spi *)hw)->SPI_IMR & SPI_IMR_TDRE) >> SPI_IMR_TDRE_Pos; in hri_spi_get_IMR_TDRE_bit()117 return (((Spi *)hw)->SPI_IMR & SPI_IMR_MODF) >> SPI_IMR_MODF_Pos; in hri_spi_get_IMR_MODF_bit()141 return (((Spi *)hw)->SPI_IMR & SPI_IMR_OVRES) >> SPI_IMR_OVRES_Pos; in hri_spi_get_IMR_OVRES_bit()165 return (((Spi *)hw)->SPI_IMR & SPI_IMR_NSSR) >> SPI_IMR_NSSR_Pos; in hri_spi_get_IMR_NSSR_bit()189 return (((Spi *)hw)->SPI_IMR & SPI_IMR_TXEMPTY) >> SPI_IMR_TXEMPTY_Pos; in hri_spi_get_IMR_TXEMPTY_bit()213 return (((Spi *)hw)->SPI_IMR & SPI_IMR_UNDES) >> SPI_IMR_UNDES_Pos; in hri_spi_get_IMR_UNDES_bit()238 tmp = ((Spi *)hw)->SPI_IMR; in hri_spi_get_IMR_reg()245 return ((Spi *)hw)->SPI_IMR; in hri_spi_read_IMR_reg()
553 __I uint32_t SPI_IMR; /**< (SPI Offset: 0x1C) Interrupt Mask Register */ member571 …__I SPI_IMR_Type SPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Reg… member
191 AT91S_REG SPI_IMR; // Interrupt Mask Register member
853 AT91_REG SPI_IMR; // Interrupt Mask Register member876 #define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register macro
3014 AT91C_REG SPI_IMR; // Interrupt Mask Register member3037 #define SPI_IMR (AT91C_CAST(AT91C_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register macro
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