Searched refs:SUNXI_DMAC_PBASE (Results 1 – 5 of 5) sorted by relevance
57 #define DMA_IRQ_EN(x) (SUNXI_DMAC_PBASE + (0x00 + ((x) << 2))) /* Interrupt enable reg…58 #define DMA_IRQ_STAT(x) (SUNXI_DMAC_PBASE + (0x10 + ((x) << 2))) /* Interrupt status reg…59 #define DMA_SECURE (SUNXI_DMAC_PBASE + 0x20) /* DMA security register */60 #define DMA_GATE (SUNXI_DMAC_PBASE + 0x28) /* DMA gating register */64 #define DMA_STAT (SUNXI_DMAC_PBASE + 0x30) /* DMA Status Register RO */65 #define DMA_ENABLE(x) (SUNXI_DMAC_PBASE + (0x100 + ((x + START_CHAN_OFFSET) << 6))) /* Chan…68 #define DMA_CFG(x) (SUNXI_DMAC_PBASE + (0x10C + ((x + START_CHAN_OFFSET) << 6))) /* Configur…69 #define DMA_CUR_SRC(x) (SUNXI_DMAC_PBASE + (0x110 + ((x + START_CHAN_OFFSET) << 6))) /* Curr…71 #define DMA_CNT(x) (SUNXI_DMAC_PBASE + (0x118 + ((x + START_CHAN_OFFSET) << 6))) /* Byte cou…72 #define DMA_PARA(x) (SUNXI_DMAC_PBASE + (0x11C + ((x + START_CHAN_OFFSET) << 6))) /* Paramete…[all …]
39 #define SUNXI_DMAC_PBASE (0x07091000) macro
35 #define SUNXI_DMAC_PBASE 0x03002000 macro
36 #define SUNXI_DMAC_PBASE 0x03002000 macro
36 #define SUNXI_DMAC_PBASE (0x03002000ul) macro
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