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Searched refs:SYSCTRL (Results 1 – 25 of 66) sorted by relevance

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/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/
A Dtae32f53xx_ll_sysctrl.c279 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_GPIOA_DbcClkCfg()
300 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_GPIOB_DbcClkCfg()
321 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_GPIOC_DbcClkCfg()
342 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_GPIOD_DbcClkCfg()
363 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_DFLASH_ClkCfg()
384 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_EFLASH_ClkCfg()
405 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_ADC_FuncClkCfg()
426 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_HRPWM_FuncClkCfg()
797 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_LSTMR_ClkEnRstRelease()
810 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_SYSCTRL_LSTMR_ClkDisRstAssert()
[all …]
A Dtae32f53xx_ll_adc.c507 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL); in LL_ADC_REG_Init()
508 __LL_SYSCTRL_ADCBuf_En(SYSCTRL); in LL_ADC_REG_Init()
509 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_ADC_REG_Init()
645 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL); in LL_ADC_INJ_Init()
646 __LL_SYSCTRL_ADCBuf_En(SYSCTRL); in LL_ADC_INJ_Init()
647 __LL_SYSCTRL_Reg_Lock(SYSCTRL); in LL_ADC_INJ_Init()
1314 Calib_read_data[0] = SYSCTRL->SINGLE; in LL_ADC_ReadCoef()
1315 Calib_read_data[1] = SYSCTRL->DIFFER; in LL_ADC_ReadCoef()
1316 Calib_read_data[2] = SYSCTRL->SINGLE_BUFF; in LL_ADC_ReadCoef()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/
A Dclock.c163 SYSCTRL->DFLLCTRL.reg = 0; in _system_clock_source_dfll_set_config_errata_9905()
245 SYSCTRL->OSC8M = temp; in system_clock_source_osc8m_set_config()
269 SYSCTRL->OSC32K = temp; in system_clock_source_osc32k_set_config()
318 SYSCTRL->XOSC = temp; in system_clock_source_xosc_set_config()
354 SYSCTRL->XOSC32K = temp; in system_clock_source_xosc32k_set_config()
437 SYSCTRL->DPLLCTRLA.reg = in system_clock_source_dpll_set_config()
441 SYSCTRL->DPLLRATIO.reg = in system_clock_source_dpll_set_config()
445 SYSCTRL->DPLLCTRLB.reg = in system_clock_source_dpll_set_config()
685 return ((SYSCTRL->DPLLSTATUS.reg & in system_clock_source_is_ready()
821 SYSCTRL->XOSC32K.bit.ONDEMAND = 1; in system_clock_init()
[all …]
/bsp/airm2m/air105/board/
A Dboard.c31 …SYSCTRL->FREQ_SEL = 0x20000000 | SYSCTRL_FREQ_SEL_HCLK_DIV_1_2 | (1 << 13) | SYSCTRL_FREQ_SEL_CLOC… in SystemInit()
33 …SYSCTRL->FREQ_SEL = 0x20000000 | SYSCTRL_FREQ_SEL_HCLK_DIV_1_2 | (1 << 13) | SYSCTRL_FREQ_SEL_CLOC… in SystemInit()
36 SYSCTRL->CG_CTRL1 = SYSCTRL_APBPeriph_ALL; in SystemInit()
37 SYSCTRL->SOFT_RST1 = SYSCTRL_APBPeriph_ALL; in SystemInit()
38 SYSCTRL->PHER_CTRL &= ~(1 << 20); in SystemInit()
39 SYSCTRL->SOFT_RST2 &= ~SYSCTRL_USB_RESET; in SystemInit()
40 SYSCTRL->LOCK_R |= SYSCTRL_USB_RESET; in SystemInit()
46 …SystemCoreClock = HSE_VALUE * (((SYSCTRL->FREQ_SEL & SYSCTRL_FREQ_SEL_XTAL_Mask) >> SYSCTRL_FREQ_S… in SystemCoreClockUpdate()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/
A Dclock.c193 SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; in system_clock_source_osc8m_set_config()
200 SYSCTRL->OSC8M = temp; in system_clock_source_osc8m_set_config()
214 SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; in system_clock_source_osc32k_set_config()
224 SYSCTRL->OSC32K = temp; in system_clock_source_osc32k_set_config()
239 SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; in system_clock_source_xosc_set_config()
273 SYSCTRL->XOSC = temp; in system_clock_source_xosc_set_config()
309 SYSCTRL->XOSC32K = temp; in system_clock_source_xosc32k_set_config()
453 SYSCTRL->OSC8M.bit.FRANGE = freq_range; in system_clock_source_write_calibration()
755 SYSCTRL->XOSC32K.bit.ONDEMAND = 1; in system_clock_init()
762 SYSCTRL->OSC32K.bit.CALIB = in system_clock_init()
[all …]
/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_otp.c30 SYSCTRL->CG_CTRL2 |= SYSCTRL_AHBPeriph_OTP; in OTP_Write()
43 SYSCTRL->CG_CTRL2 &= ~SYSCTRL_AHBPeriph_OTP; in OTP_Write()
48 SYSCTRL->CG_CTRL2 |= SYSCTRL_AHBPeriph_OTP; in OTP_Read()
52 SYSCTRL->CG_CTRL2 &= ~SYSCTRL_AHBPeriph_OTP; in OTP_Read()
56 SYSCTRL->CG_CTRL2 |= SYSCTRL_AHBPeriph_OTP; in OTP_Lock()
61 SYSCTRL->CG_CTRL2 &= ~SYSCTRL_AHBPeriph_OTP; in OTP_Lock()
A Dcore_dma.c238 …SYSCTRL->DMA_CHAN = (SYSCTRL->DMA_CHAN & ~(0x0000003f << tmpChannelxBit)) | (DMA_InitStruct->DMA_P… in DMA_ConfigStream()
243 …SYSCTRL->DMA_CHAN1 = (SYSCTRL->DMA_CHAN1 & ~(0x0000003f << tmpChannelxBit)) | (DMA_InitStruct->DMA… in DMA_ConfigStream()
387 …DBG("global 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", SYSCTRL->DMA_CHAN, SYSCTRL->DMA_CHAN1, DMA->Statu… in DMA_PrintGlobalReg()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/
A Dbod_feature.h267 SYSCTRL->BOD33.reg |= SYSCTRL_BOD33_ENABLE; in bod_enable()
294 …SYSCTRL->INTENCLR.reg = SYSCTRL_INTENCLR_BOD33RDY | SYSCTRL_INTENCLR_BOD33DET | SYSCTRL_INTENCLR_B… in bod_disable()
295 …SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | SYSCTRL_INTFLAG_B33SR… in bod_disable()
296 SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE; in bod_disable()
324 return SYSCTRL->INTFLAG.bit.BOD33DET; in bod_is_detected()
344 SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET; in bod_clear_detected()
A Dbod.c71 if (SYSCTRL->BOD33.reg & SYSCTRL_BOD33_ENABLE) { in bod_set_config()
72 SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE; in bod_set_config()
98 SYSCTRL->BOD33.reg = SYSCTRL_BOD33_LEVEL(conf->level) | temp; in bod_set_config()
100 while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_B33SRDY)) { in bod_set_config()
/bsp/apollo2/libraries/drivers/hal/
A Dam_hal_interrupt.c90 AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 1); in am_hal_interrupt_enable()
94 AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 1); in am_hal_interrupt_enable()
98 AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 1); in am_hal_interrupt_enable()
139 AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 0); in am_hal_interrupt_disable()
143 AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 0); in am_hal_interrupt_disable()
147 AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 0); in am_hal_interrupt_disable()
A Dam_hal_sysctrl.c336 AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 1); in am_hal_sysctrl_sleep()
435 AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 0); in am_hal_sysctrl_sleep()
465 AM_REG(SYSCTRL, CPACR) = (AM_REG_SYSCTRL_CPACR_CP11(0x3) | in am_hal_sysctrl_fpu_enable()
485 AM_REG(SYSCTRL, CPACR) = 0x00000000 & in am_hal_sysctrl_fpu_disable()
521 AM_REG(SYSCTRL, FPCCR) |= (AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) | in am_hal_sysctrl_fpu_stacking_enable()
529 AM_REG(SYSCTRL, FPCCR) |= AM_REG_SYSCTRL_FPCCR_ASPEN(0x1); in am_hal_sysctrl_fpu_stacking_enable()
550 AM_REG(SYSCTRL, FPCCR) &= ~(AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) | in am_hal_sysctrl_fpu_stacking_disable()
569 AM_REG(SYSCTRL, AIRCR) = AM_REG_SYSCTRL_AIRCR_VECTKEY(0x5FA) | in am_hal_sysctrl_aircr_reset()
A Dam_hal_itm.c81 AM_REG(SYSCTRL, DEMCR) |= AM_REG_SYSCTRL_DEMCR_TRCENA(1); in am_hal_itm_enable()
82 while ( !(AM_REG(SYSCTRL, DEMCR) & AM_REG_SYSCTRL_DEMCR_TRCENA(1)) ); in am_hal_itm_enable()
153 AM_REG(SYSCTRL, DEMCR) &= ~AM_REG_SYSCTRL_DEMCR_TRCENA(1); in am_hal_itm_disable()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/
A Dpower.h114 SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN; in system_voltage_reference_enable()
118 SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN; in system_voltage_reference_enable()
139 SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN; in system_voltage_reference_disable()
143 SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; in system_voltage_reference_disable()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/
A Dsamd20e14.h366 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
444 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
446 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20e15.h366 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
444 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
446 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20g14.h373 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
453 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
455 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20g15.h373 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
453 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
455 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20g16.h373 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
453 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
455 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20g17.h373 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
453 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
455 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20g17u.h373 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
453 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
455 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20g18.h373 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
453 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
455 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20g18u.h373 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
453 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
455 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20e16.h366 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
444 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
446 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20e17.h366 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
444 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
446 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
A Dsamd20e18.h366 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
444 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ macro
446 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */

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