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/bsp/ti/c28x/libraries/tms320f28379d/common/source/
A DF2837xD_CpuTimers.c82 CpuTimer0Regs.TCR.bit.TSS = 1; in InitCpuTimers()
87 CpuTimer0Regs.TCR.bit.TRB = 1; in InitCpuTimers()
117 CpuTimer1Regs.TCR.bit.TSS = 1; in InitCpuTimers()
118 CpuTimer2Regs.TCR.bit.TSS = 1; in InitCpuTimers()
123 CpuTimer1Regs.TCR.bit.TRB = 1; in InitCpuTimers()
124 CpuTimer2Regs.TCR.bit.TRB = 1; in InitCpuTimers()
164 Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart in ConfigCpuTimer()
166 Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer in ConfigCpuTimer()
167 Timer->RegsAddr->TCR.bit.SOFT = 0; in ConfigCpuTimer()
168 Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled in ConfigCpuTimer()
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A DF2837xD_SysCtrl.c738 t1TCR = CpuTimer1Regs.TCR.all; in InitSysPll()
744 t2TCR = CpuTimer2Regs.TCR.all; in InitSysPll()
800 while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0)); in InitSysPll()
813 CpuTimer1Regs.TCR.all = t1TCR; in InitSysPll()
819 CpuTimer2Regs.TCR.all = t2TCR; in InitSysPll()
936 t2TCR = CpuTimer2Regs.TCR.all; in InitAuxPll()
1012 if(CpuTimer2Regs.TCR.bit.TIF) in InitAuxPll()
1017 CpuTimer2Regs.TCR.bit.TIF = 1; in InitAuxPll()
1030 CpuTimer2Regs.TCR.bit.TSS = 1; in InitAuxPll()
1103 CpuTimer2Regs.TCR.all = t2TCR; in InitAuxPll()
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/bsp/ti/c28x/libraries/tms320f28379d/common/include/
A DF2837xD_cputimervars.h71 #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
76 #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
81 #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
96 #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
97 #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
102 #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
103 #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
108 #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
109 #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
A DF2837xD_Examples.h388 #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
393 #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
398 #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
413 #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
414 #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
419 #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
420 #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
425 #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
426 #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/
A Ddw_timer_ll.h95 timer_base->TCR |= (DW_TIMER_CTL_ENABLE_SEL_EN); in dw_timer_set_enable()
99 timer_base->TCR &= ~(DW_TIMER_CTL_ENABLE_SEL_EN); in dw_timer_set_disable()
107 timer_base->TCR &= ~(DW_TIMER_CTL_MODE_SEL_EN); in dw_timer_set_mode_free()
111 timer_base->TCR |= (DW_TIMER_CTL_MODE_SEL_EN); in dw_timer_set_mode_load()
115 return (((timer_base->TCR) & DW_TIMER_CTL_MODE_SEL_EN) ? (uint32_t)1 : (uint32_t)0); in dw_timer_get_model()
119 timer_base->TCR |= (DW_TIMER_CTL_INT_MAKS_EN); in dw_timer_set_mask()
123 timer_base->TCR &= ~(DW_TIMER_CTL_INT_MAKS_EN); in dw_timer_set_unmask()
127 return (((timer_base->TCR) & DW_TIMER_CTL_INT_MAKS_EN) ? (uint32_t)1 : (uint32_t)0); in dw_timer_get_mask()
131 timer_base->TCR |= (DW_TIMER_CTL_HARD_TRIG_EN); in dw_timer_set_hardtrigger_en()
135 timer_base->TCR &= ~(DW_TIMER_CTL_HARD_TRIG_EN); in dw_timer_set_hardtrigger_dis()
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/bsp/cvitek/drivers/
A Ddrv_timer.c236 timer_base->TCR |= (DW_TIMER_CTL_ENABLE_SEL_EN); in hal_timer_set_enable()
240 timer_base->TCR &= ~(DW_TIMER_CTL_ENABLE_SEL_EN); in hal_timer_set_disable()
251 timer_base->TCR &= ~(DW_TIMER_CTL_MODE_SEL_EN); in hal_timer_set_mode_free()
255 timer_base->TCR |= (DW_TIMER_CTL_MODE_SEL_EN); in hal_timer_set_mode_load()
259 if ((timer_base->TCR) & DW_TIMER_CTL_MODE_SEL_EN) in hal_timer_get_model()
266 timer_base->TCR |= (DW_TIMER_CTL_INT_MAKS_EN); in hal_timer_set_mask()
270 timer_base->TCR &= ~(DW_TIMER_CTL_INT_MAKS_EN); in hal_timer_set_unmask()
274 if ((timer_base->TCR) & DW_TIMER_CTL_INT_MAKS_EN) in hal_timer_get_mask()
281 timer_base->TCR |= (DW_TIMER_CTL_HARD_TRIG_EN); in hal_timer_set_hardtrigger_en()
285 timer_base->TCR &= ~(DW_TIMER_CTL_HARD_TRIG_EN); in hal_timer_set_hardtrigger_dis()
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/bsp/tms320c6678/common/
A Dcommon.c62 gp_timer_regs[timer_num]->TCR= 0; in reset_timer()
131 gp_timer_regs[tmrCfg->timer_num]->TCR = in timer64_init()
149 gp_timer_regs[tmrCfg->timer_num]->TCR = in timer64_init()
163 gp_timer_regs[tmrCfg->timer_num]->TCR = in timer64_init()
177 gp_timer_regs[tmrCfg->timer_num]->TCR = in timer64_init()
191 gp_timer_regs[tmrCfg->timer_num]->TCR = in timer64_init()
A Dcommon.h37 volatile unsigned int TCR; member
/bsp/apollo2/libraries/drivers/hal/
A Dam_hal_itm.c138 while ( AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1) ); in am_hal_itm_disable()
145 AM_REG(ITM, TCR) &= ~AM_REG_ITM_TCR_ITM_ENABLE(1); in am_hal_itm_disable()
146 while ( AM_REG(ITM, TCR) & (AM_REG_ITM_TCR_ITM_ENABLE(1) | AM_REG_ITM_TCR_BUSY(1)) ); in am_hal_itm_disable()
178 while (AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1)); in am_hal_itm_not_busy()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_lpspi.c206 base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | in LPSPI_MasterInit()
268 base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | in LPSPI_SlaveInit()
612 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_MasterTransferBlocking()
660 base->TCR = in LPSPI_MasterTransferBlocking()
722 base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); in LPSPI_MasterTransferBlocking()
761 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_MasterTransferNonBlocking()
837 base->TCR = in LPSPI_MasterTransferNonBlocking()
935 base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); in LPSPI_MasterTransferFillUpTxFifo()
1077 base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); in LPSPI_MasterTransferHandleIRQ()
1132 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_SlaveTransferNonBlocking()
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A Dfsl_lpspi_edma.c166 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_MasterTransferEDMA()
245 …base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSP… in LPSPI_MasterTransferEDMA()
412 handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); in LPSPI_MasterTransferEDMA()
417 transferConfigTx.destAddr = (uint32_t) & (base->TCR); in LPSPI_MasterTransferEDMA()
618 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; in LPSPI_SlaveTransferEDMA()
696 base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) | in LPSPI_SlaveTransferEDMA()
A Dfsl_dac.h369 base->TCR = LPDAC_TCR_SWTRG_MASK; in DAC_DoSoftwareTriggerFIFO()
A Dfsl_lpspi.h791 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1); in LPSPI_SetFrameSize()
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_uart.h570 #define __LL_UART_TxMode_Set(__UART__, mode) MODIFY_REG((__UART__)->TCR, UART_TCR_XFER_MODE_…
577 #define __LL_UART_DE_ActHigh_Set(__UART__) SET_BIT((__UART__)->TCR, UART_TCR_DE_POL_Msk)
584 #define __LL_UART_DE_ActLow_Set(__UART__) CLEAR_BIT((__UART__)->TCR, UART_TCR_DE_POL_Msk)
591 #define __LL_UART_RE_ActHigh_Set(__UART__) SET_BIT((__UART__)->TCR, UART_TCR_RE_POL_Msk)
598 #define __LL_UART_RE_ActLow_Set(__UART__) CLEAR_BIT((__UART__)->TCR, UART_TCR_RE_POL_Msk)
605 #define __LL_UART_RS485Mode_En(__UART__) SET_BIT((__UART__)->TCR, UART_TCR_RS485_EN_Msk)
612 #define __LL_UART_RS485Mode_Dis(__UART__) CLEAR_BIT((__UART__)->TCR, UART_TCR_RS485_EN_Ms…
A Dtae32f53xx_ll_dma.h937 #define __LL_DMA_Ch1TransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->TCR, DMA_TCR_TC_CH…
944 #define __LL_DMA_Ch0TransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->TCR, DMA_TCR_TC_CH…
952 #define __LL_DMA_RegTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->TCR, val)
/bsp/ti/c28x/tms320f28379d/board/
A Dboard.c33 CpuTimer2Regs.TCR.all = 0xC000; in cpu_timer2_isr()
87 CpuTimer2Regs.TCR.all = 0x4000; in rt_hw_board_init()
/bsp/ck802/libraries/common/trng/
A Dck_trng.h36 __IOM uint32_t TCR; /* Offset: 0x000 (W/R) TRNG control register */ member
A Dck_trng.c59 trng_reg->TCR |= TRNG_EN; in trng_enable()
71 int flag = (trng_reg->TCR & TRNG_DATA_READY); in trng_data_is_ready()
/bsp/dm365/platform/
A Ddm365_timer.h20 #define TCR 0x20 macro
A Ddm365.c319 davinci_writel(0, base + TCR); in reset_system()
335 davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR); in reset_system()
/bsp/efm32/EFM32_Gxxx_DK/
A Dtrace.c86 ITM->TCR = 0x10009; in TRACE_SWOSetup()
/bsp/ti/c28x/libraries/tms320f28379d/headers/include/
A DF2837xD_cputimer.h114 …union TCR_REG TCR; // CPU-Timer, Control Regis… member
/bsp/efm32/EFM32GG_DK3750/
A Dtrace.c121 ITM->TCR = 0x10009; in TRACE_SWOSetup()
/bsp/nxp/mcx/mcxn/Libraries/drivers/
A Ddrv_pwm.c207 if ((ct->TCR & CTIMER_TCR_CEN_MASK) == 0U) in mcx_drv_pwm_set()
248 ct->TCR |= CTIMER_TCR_CEN_MASK; in mcx_drv_pwm_set()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_sled.c85 SLEDx->TCR = (SLED_InitStruct->TRST << 16) in SLED_Init()

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