Searched refs:TCTRL (Results 1 – 13 of 13) sorted by relevance
| /bsp/frdm-k64f/device/MK64F12/ |
| A D | fsl_pit.h | 156 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
160 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
183 base->CHANNEL[channel].TCTRL |= mask; in PIT_EnableInterrupts()
196 base->CHANNEL[channel].TCTRL &= ~mask; in PIT_DisableInterrupts()
210 return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); in PIT_GetEnabledInterrupts()
310 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; in PIT_StartTimer()
324 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; in PIT_StopTimer()
|
| /bsp/nv32f100x/lib/inc/ |
| A D | pit.h | 176 PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_TEN_MASK; in PIT_ChannelEnable()
193 PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; in PIT_ChannelDisable()
211 PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_TIE_MASK; in PIT_ChannelEnableInt()
229 PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_TIE_MASK; in PIT_ChannelDisableInt()
245 PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_CHN_MASK; in PIT_ChannelEnableChain()
262 PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; in PIT_ChannelDisableChain()
|
| A D | NV32.h | 1779 …__IO uint32_t TCTRL; /**< ETMer Control Register, array offset: 0x108,… member
|
| /bsp/allwinner_tina/drivers/spi/ |
| A D | drv_spi.c | 86 HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_XCH_MASK); in SPI_StartTransmit()
95 HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_FBS_MASK, bit); in SPI_SetFirstTransmitBit()
104 HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_RPSM_MASK); in SPI_EnableRapidsMode()
114 HAL_CLR_BIT(spi->TCTRL, SPI_TCTRL_RPSM_MASK); in SPI_DisableRapidsMode()
123 HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_DHB_MASK, duplex); in SPI_SetDuplex()
141 HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK); in SPI_ManualChipSelect()
142 HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs); in SPI_ManualChipSelect()
151 HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs); in SPI_AutoChipSelect()
152 HAL_CLR_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK); in SPI_AutoChipSelect()
162 HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SPOL_MASK, (!!idle) << SPI_TCTRL_SPOL_SHIFT); in SPI_SetCsIdle()
[all …]
|
| A D | drv_spi.h | 29 …volatile rt_uint32_t TCTRL; /* SPI Transfer Control Register, A… member
|
| /bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/ |
| A D | fsl_lpadc.c | 186 base->TCTRL[triggerId] = tmp32; in LPADC_SetConvTriggerConfig()
310 mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ in LPADC_DoAutoCalibration()
335 base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ in LPADC_DoAutoCalibration()
|
| A D | fsl_lpit.c | 131 base->CHANNEL[channel].TCTRL = reg; in LPIT_SetupChannel()
|
| /bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/ |
| A D | tae32f53xx_ll_can.h | 471 #define __LL_CAN_FD_ISO_En(__CAN__) SET_BIT((__CAN__)->TCTRL, CAN_FD_ISO_Msk)
478 #define __LL_CAN_FD_ISO_Dis(__CAN__) CLEAR_BIT((__CAN__)->TCTRL, CAN_FD_ISO_Msk)
485 #define __LL_CAN_TxSecNext_Set(__CAN__) SET_BIT((__CAN__)->TCTRL, CAN_TX_SEC_NEXT_Msk)
492 #define __LL_CAN_TxSecSta_Get(__CAN__) (READ_BIT((__CAN__)->TCTRL, CAN_TX_SEC_STA_Msk)…
|
| /bsp/acm32/acm32f4xx-nucleo/libraries/Device/ |
| A D | ACM32F4.h | 165 __IO uint32_t TCTRL; member
|
| /bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Include/ |
| A D | tae32f53xx.h | 840 …__IO uint8_t TCTRL; /*!< Address offset: 0x92: Transmit Control Register … member
|
| /bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/ |
| A D | RV32M1_ri5cy.h | 665 …__IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xC0… member
11209 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, … member
|
| A D | RV32M1_zero_riscy.h | 635 …__IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xC0… member
11352 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, … member
|
| /bsp/frdm-k64f/device/ |
| A D | MK64F12.h | 8699 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
|
Completed in 972 milliseconds