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Searched refs:TC_CTRLA_ENABLE (Results 1 – 15 of 15) sorted by relevance

/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/
A Dtc.c198 if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { in tc_init()
617 if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { in tc_reset()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/
A Dtc.c200 if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { in tc_init()
643 if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { in tc_reset()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/
A Dtc.h1258 tc_module->CTRLA.reg |= TC_CTRLA_ENABLE; in tc_enable()
1288 tc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; in tc_disable()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Dtc.h81 #define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) macro
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/
A Dtcc.h1797 tcc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; in tcc_disable()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/
A Dtc.h84 #define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) macro
/bsp/microchip/samc21/bsp/hri/
A Dhri_tc_c21.h515 ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; in hri_tc_set_CTRLA_ENABLE_bit()
525 tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; in hri_tc_get_CTRLA_ENABLE_bit()
534 tmp &= ~TC_CTRLA_ENABLE; in hri_tc_write_CTRLA_ENABLE_bit()
544 ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; in hri_tc_clear_CTRLA_ENABLE_bit()
552 ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; in hri_tc_toggle_CTRLA_ENABLE_bit()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_tc_d51.h515 ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; in hri_tc_set_CTRLA_ENABLE_bit()
525 tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; in hri_tc_get_CTRLA_ENABLE_bit()
534 tmp &= ~TC_CTRLA_ENABLE; in hri_tc_write_CTRLA_ENABLE_bit()
544 ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; in hri_tc_clear_CTRLA_ENABLE_bit()
552 ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; in hri_tc_toggle_CTRLA_ENABLE_bit()
/bsp/microchip/same54/bsp/hri/
A Dhri_tc_e54.h515 ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; in hri_tc_set_CTRLA_ENABLE_bit()
525 tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; in hri_tc_get_CTRLA_ENABLE_bit()
534 tmp &= ~TC_CTRLA_ENABLE; in hri_tc_write_CTRLA_ENABLE_bit()
544 ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; in hri_tc_clear_CTRLA_ENABLE_bit()
552 ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; in hri_tc_toggle_CTRLA_ENABLE_bit()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_tc_d51.h515 ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; in hri_tc_set_CTRLA_ENABLE_bit()
525 tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; in hri_tc_get_CTRLA_ENABLE_bit()
534 tmp &= ~TC_CTRLA_ENABLE; in hri_tc_write_CTRLA_ENABLE_bit()
544 ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; in hri_tc_clear_CTRLA_ENABLE_bit()
552 ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; in hri_tc_toggle_CTRLA_ENABLE_bit()
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dtc.h79 #define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos) macro
/bsp/microchip/same54/bsp/include/component/
A Dtc.h83 #define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos) macro
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dtc.h83 #define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos) macro
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dtc.h83 #define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos) macro
/bsp/microchip/saml10/bsp/include/component/
A Dtc.h88 #define TC_CTRLA_ENABLE TC_CTRLA_ENABLE_Msk /**< \de… macro

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