Searched refs:TC_DRVCTRL_INVEN0 (Results 1 – 9 of 9) sorted by relevance
1449 ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; in hri_tc_set_DRVCTRL_INVEN0_bit()1457 tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; in hri_tc_get_DRVCTRL_INVEN0_bit()1466 tmp &= ~TC_DRVCTRL_INVEN0; in hri_tc_write_DRVCTRL_INVEN0_bit()1475 ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; in hri_tc_clear_DRVCTRL_INVEN0_bit()1482 ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; in hri_tc_toggle_DRVCTRL_INVEN0_bit()
1553 ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; in hri_tc_set_DRVCTRL_INVEN0_bit()1561 tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; in hri_tc_get_DRVCTRL_INVEN0_bit()1570 tmp &= ~TC_DRVCTRL_INVEN0; in hri_tc_write_DRVCTRL_INVEN0_bit()1579 ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; in hri_tc_clear_DRVCTRL_INVEN0_bit()1586 ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; in hri_tc_toggle_DRVCTRL_INVEN0_bit()
474 #define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos) macro
496 #define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos) macro
555 #define TC_DRVCTRL_INVEN0 TC_DRVCTRL_INVEN0_Msk /**< \de… macro
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