1 /* 2 * Copyright (C) 2019 ETH Zurich and University of Bologna 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 * 16 * SPDX-License-Identifier: Apache-2.0 17 */ 18 19 /* Author: Robert Balas (balasr@iis.ee.ethz.ch) 20 * Germain Haugou (germain.haugou@iis.ee.ethz.ch) 21 */ 22 23 #ifndef HAL_INCLUDE_HAL_TIMER_H_ 24 #define HAL_INCLUDE_HAL_TIMER_H_ 25 26 #include "bits.h" 27 28 /* Timer Low Configuration register. */ 29 #define TIMER_CFG_LO_OFFSET 0x0 30 31 /* Timer High Configuration register. */ 32 #define TIMER_CFG_HI_OFFSET 0x4 33 34 /* Timer Low counter value register. */ 35 #define TIMER_CNT_LO_OFFSET 0x8 36 37 /* Timer High counter value register. */ 38 #define TIMER_CNT_HI_OFFSET 0xc 39 40 /* Timer Low comparator value register. */ 41 #define TIMER_CMP_LO_OFFSET 0x10 42 43 /* Timer High comparator value register. */ 44 #define TIMER_CMP_HI_OFFSET 0x14 45 46 /* Start Timer Low counting register. */ 47 #define TIMER_START_LO_OFFSET 0x18 48 49 /* Start Timer High counting register. */ 50 #define TIMER_START_HI_OFFSET 0x1c 51 52 /* Reset Timer Low counter register. */ 53 #define TIMER_RESET_LO_OFFSET 0x20 54 55 /* Reset Timer High counter register. */ 56 #define TIMER_RESET_HI_OFFSET 0x24 57 58 /* Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled 59 * (access: R/W) */ 60 #define TIMER_CFG_LO_ENABLE_BIT 0 61 #define TIMER_CFG_LO_ENABLE_WIDTH 1 62 #define TIMER_CFG_LO_ENABLE_MASK 0x1 63 64 /* Timer low counter reset command bitfield. Cleared after Timer Low reset 65 * execution. (access: R/W) */ 66 #define TIMER_CFG_LO_RESET_BIT 1 67 #define TIMER_CFG_LO_RESET_WIDTH 1 68 #define TIMER_CFG_LO_RESET_MASK 0x2 69 70 /* Timer low compare match interrupt enable configuration bitfield: - 1'b0: 71 * disabled - 1'b1: enabled (access: R/W) */ 72 #define TIMER_CFG_LO_IRQEN_BIT 2 73 #define TIMER_CFG_LO_IRQEN_WIDTH 1 74 #define TIMER_CFG_LO_IRQEN_MASK 0x4 75 76 /* Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1: 77 * enabled (access: R/W) */ 78 #define TIMER_CFG_LO_IEM_BIT 3 79 #define TIMER_CFG_LO_IEM_WIDTH 1 80 #define TIMER_CFG_LO_IEM_MASK 0x8 81 82 /* Timer low continuous mode configuration bitfield: - 1'b0: Continue mode - 83 * continue incrementing Timer low counter when compare match with CMP_LO 84 * occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with 85 * CMP_LO occurs. (access: R/W) */ 86 #define TIMER_CFG_LO_MODE_BIT 4 87 #define TIMER_CFG_LO_MODE_WIDTH 1 88 #define TIMER_CFG_LO_MODE_MASK 0x10 89 90 /* Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled 91 * counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low 92 * when compare match with CMP_LO occurs. (access: R/W) */ 93 #define TIMER_CFG_LO_ONE_S_BIT 5 94 #define TIMER_CFG_LO_ONE_S_WIDTH 1 95 #define TIMER_CFG_LO_ONE_S_MASK 0x20 96 97 /* Timer low prescaler enable configuration bitfield:- 1'b0: disabled - 1'b1: 98 * enabled (access: R/W) */ 99 #define TIMER_CFG_LO_PEN_BIT 6 100 #define TIMER_CFG_LO_PEN_WIDTH 1 101 #define TIMER_CFG_LO_PEN_MASK 0x40 102 103 /* Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz (access: R/W) */ 104 #define TIMER_CFG_LO_CCFG_BIT 7 105 #define TIMER_CFG_LO_CCFG_WIDTH 1 106 #define TIMER_CFG_LO_CCFG_MASK 0x80 107 108 /* Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL) (access: 109 * R/W) */ 110 #define TIMER_CFG_LO_PVAL_BIT 8 111 #define TIMER_CFG_LO_PVAL_WIDTH 8 112 #define TIMER_CFG_LO_PVAL_MASK 0xff00 113 114 /* Timer low + Timer high 64bit cascaded mode configuration bitfield. (access: 115 * R/W) */ 116 #define TIMER_CFG_LO_CASC_BIT 31 117 #define TIMER_CFG_LO_CASC_WIDTH 1 118 #define TIMER_CFG_LO_CASC_MASK 0x80000000 119 120 /* Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled 121 * (access: R/W) */ 122 #define TIMER_CFG_HI_ENABLE_BIT 0 123 #define TIMER_CFG_HI_ENABLE_WIDTH 1 124 #define TIMER_CFG_HI_ENABLE_MASK 0x1 125 126 /* Timer high counter reset command bitfield. Cleared after Timer high reset 127 * execution. (access: W) */ 128 #define TIMER_CFG_HI_RESET_BIT 1 129 #define TIMER_CFG_HI_RESET_WIDTH 1 130 #define TIMER_CFG_HI_RESET_MASK 0x2 131 132 /* Timer high compare match interrupt enable configuration bitfield: - 1'b0: 133 * disabled - 1'b1: enabled (access: R/W) */ 134 #define TIMER_CFG_HI_IRQEN_BIT 2 135 #define TIMER_CFG_HI_IRQEN_WIDTH 1 136 #define TIMER_CFG_HI_IRQEN_MASK 0x4 137 138 /* Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1: 139 * enabled (access: R/W) */ 140 #define TIMER_CFG_HI_IEM_BIT 3 141 #define TIMER_CFG_HI_IEM_WIDTH 1 142 #define TIMER_CFG_HI_IEM_MASK 0x8 143 144 /* Timer high continuous mode configuration bitfield: - 1'b0: Continue mode - 145 * continue incrementing Timer high counter when compare match with CMP_LO 146 * occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with 147 * CMP_LO occurs. (access: R/W) */ 148 #define TIMER_CFG_HI_MODE_BIT 4 149 #define TIMER_CFG_HI_MODE_WIDTH 1 150 #define TIMER_CFG_HI_MODE_MASK 0x10 151 152 /* Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled 153 * counting when compare match with CMP_LO occurs. - 1'b1: disable Timer high 154 * when compare match with CMP_LO occurs. (access: R/W) */ 155 #define TIMER_CFG_HI_ONE_S_BIT 5 156 #define TIMER_CFG_HI_ONE_S_WIDTH 1 157 #define TIMER_CFG_HI_ONE_S_MASK 0x20 158 159 /* Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: 160 * enabled (access: R/W) */ 161 #define TIMER_CFG_HI_PEN_BIT 6 162 #define TIMER_CFG_HI_PEN_WIDTH 1 163 #define TIMER_CFG_HI_PEN_MASK 0x40 164 165 166 /* Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler 167 * - 1'b1: Reference clock at 32kHz (access: R/W) */ 168 #define TIMER_CFG_HI_CCFG_BIT 7 169 #define TIMER_CFG_HI_CCFG_WIDTH 1 170 #define TIMER_CFG_HI_CCFG_MASK 0x80 171 172 /* Timer Low counter value bitfield. (access: R/W) */ 173 #define TIMER_CNT_LO_CNT_LO_BIT 0 174 #define TIMER_CNT_LO_CNT_LO_WIDTH 32 175 #define TIMER_CNT_LO_CNT_LO_MASK 0xffffffff 176 177 /* Timer High counter value bitfield. (access: R/W) */ 178 #define TIMER_CNT_HI_CNT_HI_BIT 0 179 #define TIMER_CNT_HI_CNT_HI_WIDTH 32 180 #define TIMER_CNT_HI_CNT_HI_MASK 0xffffffff 181 182 /* Timer Low comparator value bitfield. (access: R/W) */ 183 #define TIMER_CMP_LO_CMP_LO_BIT 0 184 #define TIMER_CMP_LO_CMP_LO_WIDTH 32 185 #define TIMER_CMP_LO_CMP_LO_MASK 0xffffffff 186 187 /* Timer High comparator value bitfield. (access: R/W) */ 188 #define TIMER_CMP_HI_CMP_HI_BIT 0 189 #define TIMER_CMP_HI_CMP_HI_WIDTH 32 190 #define TIMER_CMP_HI_CMP_HI_MASK 0xffffffff 191 192 /* Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set. 193 * (access: W) */ 194 #define TIMER_START_LO_STRT_LO_BIT 0 195 #define TIMER_START_LO_STRT_LO_WIDTH 1 196 #define TIMER_START_LO_STRT_LO_MASK 0x1 197 198 /* Timer High start command bitfield. When executed, CFG_HI.ENABLE is set. 199 * (access: W) */ 200 #define TIMER_START_HI_STRT_HI_BIT 0 201 #define TIMER_START_HI_STRT_HI_WIDTH 1 202 #define TIMER_START_HI_STRT_HI_MASK 0x1 203 204 /* Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set. 205 * (access: W) */ 206 #define TIMER_RESET_LO_RST_LO_BIT 0 207 #define TIMER_RESET_LO_RST_LO_WIDTH 1 208 #define TIMER_RESET_LO_RST_LO_MASK 0x1 209 210 /* Timer High counter reset command bitfield. When executed, CFG_HI.RESET is 211 * set. (access: W) */ 212 #define TIMER_RESET_HI_RST_HI_BIT 0 213 #define TIMER_RESET_HI_RST_HI_WIDTH 1 214 #define TIMER_RESET_HI_RST_HI_MASK 0x1 215 216 struct pulp_timer { 217 unsigned int current_time; 218 unsigned int flags; 219 void *base; 220 }; 221 222 223 #endif /* HAL_INCLUDE_HAL_TIMER_H_ */ 224