1 /* 2 * Copyright 2021 MindMotion Microelectronics Co., Ltd. 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef __HAL_TIM_ADV_H__ 9 #define __HAL_TIM_ADV_H__ 10 11 #include "hal_common.h" 12 13 /*! 14 * @addtogroup TIM_ADV 15 * @{ 16 */ 17 18 /*! 19 * @brief TIM_ADV driver version number. 20 */ 21 #define TIM_ADV_DRIVER_VERSION 0u /*!< TIM_ADV_0. */ 22 23 /*! 24 * @addtogroup TIM_ADV_CHANNEL_SELECTION 25 * @{ 26 */ 27 #define TIM_ADV_CHN_NUM (5u) /*!< The total number of TIM_ADV channel. */ 28 #define TIM_ADV_CHN_1 (0u) /*!< The selection of TIM_ADV Channel 1. */ 29 #define TIM_ADV_CHN_2 (1u) /*!< The selection of TIM_ADV Channel 2. */ 30 #define TIM_ADV_CHN_3 (2u) /*!< The selection of TIM_ADV Channel 3. */ 31 #define TIM_ADV_CHN_4 (3u) /*!< The selection of TIM_ADV Channel 4. */ 32 #define TIM_ADV_CHN_5 (4u) /*!< The selection of TIM_ADV Channel 5. */ 33 /*! 34 *@} 35 */ 36 37 /*! 38 * @addtogroup TIM_ADV_INT 39 * @brief Enable interrupt. 40 * @{ 41 */ 42 #define TIM_ADV_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */ 43 #define TIM_ADV_INT_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt switchers. */ 44 #define TIM_ADV_INT_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt switchers. */ 45 #define TIM_ADV_INT_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt switchers. */ 46 #define TIM_ADV_INT_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt switchers. */ 47 #define TIM_ADV_INT_COM_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt switchers. */ 48 #define TIM_ADV_INT_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt switchers. */ 49 #define TIM_ADV_INT_BREAK_EVENT (1u << 7u) /*!< Break event interrupt switchers. */ 50 #define TIM_ADV_INT_CH5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt switchers. */ 51 /*! 52 * @} 53 */ 54 55 /*! 56 * @addtogroup TIM_ADV_DMA 57 * @brief Enable DMA. 58 * @{ 59 */ 60 #define TIM_ADV_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period DMA switchers. */ 61 #define TIM_ADV_DMA_CHN1_EVENT (1u << 9u) /*!< Channel 1 event for output compare or input capture DMA switchers. */ 62 #define TIM_ADV_DMA_CHN2_EVENT (1u << 10u) /*!< Channel 2 event for output compare or input capture DMA switchers. */ 63 #define TIM_ADV_DMA_CHN3_EVENT (1u << 11u) /*!< Channel 3 event for output compare or input capture DMA switchers. */ 64 #define TIM_ADV_DMA_CHN4_EVENT (1u << 12u) /*!< Channel 4 event for output compare or input capture DMA switchers. */ 65 #define TIM_ADV_DMA_COM_EVENT (1u << 13u) /*!< Channel complementary pwm commutation interrupt switchers. */ 66 #define TIM_ADV_DMA_TRGOUT_EVENT (1u << 14u) /*!< Trigger out event DMA switchers. */ 67 /*! 68 * @} 69 */ 70 71 /*! 72 * @addtogroup TIM_ADV_INT_STATUS 73 * @brief Check interrupt status. 74 * @{ 75 */ 76 #define TIM_ADV_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */ 77 #define TIM_ADV_STATUS_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt flag. */ 78 #define TIM_ADV_STATUS_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt flag. */ 79 #define TIM_ADV_STATUS_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt flag. */ 80 #define TIM_ADV_STATUS_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt flag. */ 81 #define TIM_ADV_STATUS_COM_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt flag. */ 82 #define TIM_ADV_STATUS_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt flag. */ 83 #define TIM_ADV_STATUS_BREAK_EVENT (1u << 7u) /*!< Break event interrupt flag. */ 84 #define TIM_ADV_STATUS_CHN1_OVER_EVENT (1u << 9u) /*!< Channel 1 event for output overcompare or input overcapture interrupt flag. */ 85 #define TIM_ADV_STATUS_CHN2_OVER_EVENT (1u << 10u) /*!< Channel 2 event for output overcompare or input overcapture interrupt flag. */ 86 #define TIM_ADV_STATUS_CHN3_OVER_EVENT (1u << 11u) /*!< Channel 3 event for output overcompare or input overcapture interrupt flag. */ 87 #define TIM_ADV_STATUS_CHN4_OVER_EVENT (1u << 12u) /*!< Channel 4 event for output overcompare or input overcapture interrupt flag. */ 88 #define TIM_ADV_STATUS_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt flag. */ 89 /*! 90 * @} 91 */ 92 93 /*! 94 * @addtogroup TIM_ADV_SWTRG 95 * @brief Events to be triggered by software. 96 * @{ 97 */ 98 #define TIM_ADV_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period software trigger. */ 99 #define TIM_ADV_SWTRG_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture software trigger. */ 100 #define TIM_ADV_SWTRG_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture software trigger. */ 101 #define TIM_ADV_SWTRG_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture software trigger. */ 102 #define TIM_ADV_SWTRG_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture software trigger. */ 103 #define TIM_ADV_SWTRG_COM_EVENT (1u << 5u) /*!< Channel complementary pwm commutation software trigger. */ 104 #define TIM_ADV_SWTRG_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event software trigger. */ 105 #define TIM_ADV_SWTRG_BREAK_EVENT (1u << 7u) /*!< Break event software trigger. */ 106 #define TIM_ADV_SWTRG_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture software trigger. */ 107 /*! 108 * @} 109 */ 110 111 /*! 112 * @brief Counter period working mode. 113 */ 114 typedef enum 115 { 116 TIM_ADV_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */ 117 TIM_ADV_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */ 118 } TIM_ADV_PeriodMode_Type; 119 120 /*! 121 * @brief Counter count direction. 122 */ 123 typedef enum 124 { 125 TIM_ADV_CountMode_Increasing = 0u, /*!< Counter counts incrementally from 0 to period and generates an update. */ 126 TIM_ADV_CountMode_Decreasing = 1u, /*!< Counter counts decrementally from period to 0 and generates an update. */ 127 TIM_ADV_CountMode_CenterAligned1 = 2u, /*!< Counter counts center-aligned from 0 to period - 1 then from period to 0 and generates an update. */ 128 TIM_ADV_CountMode_CenterAligned2 = 3u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0. */ 129 TIM_ADV_CountMode_CenterAligned3 = 4u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0 and generates another update. */ 130 } TIM_ADV_CountMode_Type; 131 132 /*! 133 * @brief TIM output compare reference polairty event. 134 */ 135 typedef enum 136 { 137 TIM_ADV_OutputCompareRefOut_None = 0u, /*!< Reference will not be changed. */ 138 TIM_ADV_OutputCompareRefOut_HighOnMatch = 1u, /*!< Reference will be high when counter value equals channel value. */ 139 TIM_ADV_OutputCompareRefOut_LowOnMatch = 2u, /*!< Reference will be low when counter value equals channel value. */ 140 TIM_ADV_OutputCompareRefOut_ToggleOnMatch = 3u, /*!< Reference will toggle. */ 141 TIM_ADV_OutputCompareRefOut_LowAlways = 4u, /*!< Reference will always be low. */ 142 TIM_ADV_OutputCompareRefOut_HighAlways = 5u, /*!< Reference will always be high. */ 143 TIM_ADV_OutputCompareRefOut_FallingEdgeOnMatch = 6u, /*!< PWM mode 1. */ 144 TIM_ADV_OutputCompareRefOut_RisingEdgeOnMatch = 7u, /*!< PWM mode 2. */ 145 } TIM_ADV_OutputCompareRefOut_Type; 146 147 /*! 148 * @brief TIM input capture active edge selection and output compare active polarity selection. 149 * | conf | TIM_ADV_PinPolarity_Rising | TIM_ADV_PinPolarity_Falling | 150 * | ----------------------- | -------------------------- | --------------------------- | 151 * | input capture | detects rising edge | detects falling edge | 152 * | output compare | high polarity is active | low polarity is active | 153 * | encoder mode | input remains | input reverses | 154 * | output under idle state | output high polarity | output low polarity | 155 */ 156 typedef enum 157 { 158 TIM_ADV_PinPolarity_Disable = 0u, /*!< Disable channel. */ 159 TIM_ADV_PinPolarity_Rising = 1u, /*!< See the table above. */ 160 TIM_ADV_PinPolarity_Falling = 2u, /*!< See the table above.*/ 161 TIM_ADV_PinPolarity_RisingOrFalling = 3u, /*!< For input capture, detect both the rising and falling edge. */ 162 }TIM_ADV_PinPolarity_Type; 163 164 /*! 165 * @brief TIM Input active times to evoke capture. 166 */ 167 typedef enum 168 { 169 TIM_ADV_InputCaptureInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */ 170 TIM_ADV_InputCaptureInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */ 171 TIM_ADV_InputCaptureInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */ 172 TIM_ADV_InputCaptureInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */ 173 } TIM_ADV_InputCaptureInDiv_Type; 174 175 /*! 176 * @brief TIM Input sampling filter. 177 */ 178 typedef enum 179 { 180 TIM_ADV_InputCaptureInFilter_Alt0 = 0u, /*!< Filter swicther 0. */ 181 TIM_ADV_InputCaptureInFilter_Alt1 = 1u, /*!< Filter swicther 1. */ 182 TIM_ADV_InputCaptureInFilter_Alt2 = 2u, /*!< Filter swicther 2. */ 183 TIM_ADV_InputCaptureInFilter_Alt3 = 3u, /*!< Filter swicther 3. */ 184 TIM_ADV_InputCaptureInFilter_Alt4 = 4u, /*!< Filter swicther 4. */ 185 TIM_ADV_InputCaptureInFilter_Alt5 = 5u, /*!< Filter swicther 5. */ 186 TIM_ADV_InputCaptureInFilter_Alt6 = 6u, /*!< Filter swicther 6. */ 187 TIM_ADV_InputCaptureInFilter_Alt7 = 7u, /*!< Filter swicther 7. */ 188 TIM_ADV_InputCaptureInFilter_Alt8 = 8u, /*!< Filter swicther 8. */ 189 TIM_ADV_InputCaptureInFilter_Alt9 = 9u, /*!< Filter swicther 9. */ 190 TIM_ADV_InputCaptureInFilter_Alt10 = 10u, /*!< Filter swicther 10. */ 191 TIM_ADV_InputCaptureInFilter_Alt11 = 11u, /*!< Filter swicther 11. */ 192 TIM_ADV_InputCaptureInFilter_Alt12 = 12u, /*!< Filter swicther 12. */ 193 TIM_ADV_InputCaptureInFilter_Alt13 = 13u, /*!< Filter swicther 13. */ 194 TIM_ADV_InputCaptureInFilter_Alt14 = 14u, /*!< Filter swicther 14. */ 195 TIM_ADV_InputCaptureInFilter_Alt15 = 15u, /*!< Filter swicther 15. */ 196 } TIM_ADV_InputCaptureInFilter_Type; 197 198 /*! 199 * @brief TIM channel IO mode. 200 */ 201 typedef enum 202 { 203 TIM_ADV_ChannelIOMode_Out = 0u, /*!< Channel output. */ 204 TIM_ADV_ChannelIOMode_In = 1u, /*!< Channel input, capture signal from direct channel. */ 205 TIM_ADV_ChannelIOMode_Alt2 = 2u, /*!< Channel input, capture signal from indirect channel. */ 206 TIM_ADV_ChannelIOMode_Alt3 = 3u, /*!< Channel input, capture signal from trc. */ 207 } TIM_ADV_ChannelIOMode_Type; 208 209 /*! 210 * @brief TIM external trigger input active edge selection. 211 */ 212 typedef enum 213 { 214 TIM_ADV_ExtTriggerPinPolarity_Disable = 0u, /*!< Disable external trigger input. */ 215 TIM_ADV_ExtTriggerPinPolarity_Rising = 1u, /*!< Detect the rising edge from external trigger. */ 216 TIM_ADV_ExtTriggerPinPolarity_Falling = 2u, /*!< Detect the falling edge from external trigger. */ 217 }TIM_ADV_ExtTriggerPinPolarity_Type; 218 219 /*! 220 * @brief TIM external trigger active input times to drive counter. 221 */ 222 typedef enum 223 { 224 TIM_ADV_ExtTriggerInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */ 225 TIM_ADV_ExtTriggerInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */ 226 TIM_ADV_ExtTriggerInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */ 227 TIM_ADV_ExtTriggerInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */ 228 } TIM_ADV_ExtTriggerInDiv_Type; 229 230 /*! 231 * @brief TIM external trigger sampling filter. 232 */ 233 typedef enum 234 { 235 TIM_ADV_ExtTriggerInFilter_Alt0 = 0u, /*!< Filter swicther 0. */ 236 TIM_ADV_ExtTriggerInFilter_Alt1 = 1u, /*!< Filter swicther 1. */ 237 TIM_ADV_ExtTriggerInFilter_Alt2 = 2u, /*!< Filter swicther 2. */ 238 TIM_ADV_ExtTriggerInFilter_Alt3 = 3u, /*!< Filter swicther 3. */ 239 TIM_ADV_ExtTriggerInFilter_Alt4 = 4u, /*!< Filter swicther 4. */ 240 TIM_ADV_ExtTriggerInFilter_Alt5 = 5u, /*!< Filter swicther 5. */ 241 TIM_ADV_ExtTriggerInFilter_Alt6 = 6u, /*!< Filter swicther 6. */ 242 TIM_ADV_ExtTriggerInFilter_Alt7 = 7u, /*!< Filter swicther 7. */ 243 TIM_ADV_ExtTriggerInFilter_Alt8 = 8u, /*!< Filter swicther 8. */ 244 TIM_ADV_ExtTriggerInFilter_Alt9 = 9u, /*!< Filter swicther 9. */ 245 TIM_ADV_ExtTriggerInFilter_Alt10 = 10u, /*!< Filter swicther 10. */ 246 TIM_ADV_ExtTriggerInFilter_Alt11 = 11u, /*!< Filter swicther 11. */ 247 TIM_ADV_ExtTriggerInFilter_Alt12 = 12u, /*!< Filter swicther 12. */ 248 TIM_ADV_ExtTriggerInFilter_Alt13 = 13u, /*!< Filter swicther 13. */ 249 TIM_ADV_ExtTriggerInFilter_Alt14 = 14u, /*!< Filter swicther 14. */ 250 TIM_ADV_ExtTriggerInFilter_Alt15 = 15u, /*!< Filter swicther 15. */ 251 } TIM_ADV_ExtTriggerInFilter_Type; 252 253 /*! 254 * @brief TIM Dead area time step length. 255 */ 256 typedef enum 257 { 258 TIM_ADV_DeadAreaStep_Alt0 = 0u, /*!< Dead area step = clock source step. */ 259 TIM_ADV_DeadAreaStep_Alt1 = 1u, /*!< Dead area step = 2 * clock source step. */ 260 TIM_ADV_DeadAreaStep_Alt2 = 2u, /*!< Dead area step = 4 * clock source step. */ 261 } TIM_ADV_DeadAreaStep_Type; 262 263 /*! 264 * @brief TIM master mode output signal source. 265 */ 266 typedef enum 267 { 268 TIM_ADV_MasterOut_Alt0 = 0u, /*!< Software update period trigger signal works as master output. */ 269 TIM_ADV_MasterOut_Alt1 = 1u, /*!< Counter enable signal works as master output. */ 270 TIM_ADV_MasterOut_Alt2 = 2u, /*!< Update period event works as master output. */ 271 TIM_ADV_MasterOut_Alt3 = 3u, /*!< Channel capture or compare event works as master output. */ 272 TIM_ADV_MasterOut_Alt4 = 4u, /*!< Reference signal of channel 1 works as master output. */ 273 TIM_ADV_MasterOut_Alt5 = 5u, /*!< Reference signal of channel 2 works as master output. */ 274 TIM_ADV_MasterOut_Alt6 = 6u, /*!< Reference signal of channel 3 works as master output. */ 275 TIM_ADV_MasterOut_Alt7 = 7u, /*!< Reference signal of channel 4 works as master output. */ 276 } TIM_ADV_MasterOut_Type; 277 278 /*! 279 * @brief TIM slave mode input object source. 280 */ 281 typedef enum 282 { 283 TIM_ADV_SlaveIn_Alt0 = 0u, /*!< Internal trigger 0. */ 284 TIM_ADV_SlaveIn_Alt1 = 1u, /*!< Internal trigger 1. */ 285 TIM_ADV_SlaveIn_Alt2 = 2u, /*!< Internal trigger 2.*/ 286 TIM_ADV_SlaveIn_Alt3 = 3u, /*!< Internal trigger 3. */ 287 TIM_ADV_SlaveIn_Alt4 = 4u, /*!< Edge detector of timer input channel 1. */ 288 TIM_ADV_SlaveIn_Alt5 = 5u, /*!< Timer input channel 1. */ 289 TIM_ADV_SlaveIn_Alt6 = 6u, /*!< Timer input channel 2. */ 290 TIM_ADV_SlaveIn_Alt7 = 7u, /*!< External trigger input. */ 291 } TIM_ADV_SlaveIn_Type; 292 293 /*! 294 * @brief TIM slave mode counter response. 295 */ 296 typedef enum 297 { 298 TIM_ADV_SlaveResp_Disable = 0u, /*!< Disable the slave mode. */ 299 TIM_ADV_SlaveResp_Alt1 = 1u, /*!< Counting in encoder mode 1. */ 300 TIM_ADV_SlaveResp_Alt2 = 2u, /*!< Counting in encoder mode 2.*/ 301 TIM_ADV_SlaveResp_Alt3 = 3u, /*!< Counting in encoder mode 3. */ 302 TIM_ADV_SlaveResp_Alt4 = 4u, /*!< Reset counter. */ 303 TIM_ADV_SlaveResp_Alt5 = 5u, /*!< Counter treat the signal as a gate. */ 304 TIM_ADV_SlaveResp_Alt6 = 6u, /*!< Start the counter. */ 305 TIM_ADV_SlaveResp_Alt7 = 7u, /*!< Counter counts on rising edges. */ 306 } TIM_ADV_SlaveResp_Type; 307 308 /*! 309 * @brief TIM DMA Burst transfer base address. 310 */ 311 typedef enum 312 { 313 TIM_ADV_DMABurstBaseAddr_Alt0 = 0u, /*!< Start from CR1 register. */ 314 TIM_ADV_DMABurstBaseAddr_Alt1 = 1u, /*!< Start from CR2 register. */ 315 TIM_ADV_DMABurstBaseAddr_Alt2 = 2u, /*!< Start from SMCR register. */ 316 TIM_ADV_DMABurstBaseAddr_Alt3 = 3u, /*!< Start from DIER register. */ 317 TIM_ADV_DMABurstBaseAddr_Alt4 = 4u, /*!< Start from SR register. */ 318 TIM_ADV_DMABurstBaseAddr_Alt5 = 5u, /*!< Start from EGR register. */ 319 TIM_ADV_DMABurstBaseAddr_Alt6 = 6u, /*!< Start from CCMR1 register. */ 320 TIM_ADV_DMABurstBaseAddr_Alt7 = 7u, /*!< Start from CCMR2 register. */ 321 TIM_ADV_DMABurstBaseAddr_Alt8 = 8u, /*!< Start from CCER register. */ 322 TIM_ADV_DMABurstBaseAddr_Alt9 = 9u, /*!< Start from CNT register. */ 323 TIM_ADV_DMABurstBaseAddr_Alt10 = 10u, /*!< Start from PSC register. */ 324 TIM_ADV_DMABurstBaseAddr_Alt11 = 11u, /*!< Start from ARR register. */ 325 TIM_ADV_DMABurstBaseAddr_Alt12 = 12u, /*!< Start from CCR1 register. */ 326 TIM_ADV_DMABurstBaseAddr_Alt13 = 13u, /*!< Start from CCR2 register. */ 327 TIM_ADV_DMABurstBaseAddr_Alt14 = 14u, /*!< Start from CCR3 register. */ 328 TIM_ADV_DMABurstBaseAddr_Alt15 = 15u, /*!< Start from CCR4 register. */ 329 } TIM_ADV_DMABurstBaseAddr_Type; 330 331 /*! 332 * @brief TIM DMA Burst transfer length. 333 */ 334 typedef enum 335 { 336 TIM_ADV_DMABurstBaseLen_Alt0 = 0u, /*!< Sequentially visit 1 register from base register */ 337 TIM_ADV_DMABurstBaseLen_Alt1 = 1u, /*!< Sequentially visit 2 registers from base register */ 338 TIM_ADV_DMABurstBaseLen_Alt2 = 2u, /*!< Sequentially visit 3 registers from base register */ 339 TIM_ADV_DMABurstBaseLen_Alt3 = 3u, /*!< Sequentially visit 4 registers from base register */ 340 TIM_ADV_DMABurstBaseLen_Alt4 = 4u, /*!< Sequentially visit 5 registers from base register */ 341 TIM_ADV_DMABurstBaseLen_Alt5 = 5u, /*!< Sequentially visit 6 registers from base register */ 342 TIM_ADV_DMABurstBaseLen_Alt6 = 6u, /*!< Sequentially visit 7 registers from base register */ 343 TIM_ADV_DMABurstBaseLen_Alt7 = 7u, /*!< Sequentially visit 8 registers from base register */ 344 TIM_ADV_DMABurstBaseLen_Alt8 = 8u, /*!< Sequentially visit 9 registers from base register */ 345 TIM_ADV_DMABurstBaseLen_Alt9 = 9u, /*!< Sequentially visit 10 registers from base register */ 346 TIM_ADV_DMABurstBaseLen_Alt10 = 10u, /*!< Sequentially visit 11 registers from base register */ 347 TIM_ADV_DMABurstBaseLen_Alt11 = 11u, /*!< Sequentially visit 12 registers from base register */ 348 TIM_ADV_DMABurstBaseLen_Alt12 = 12u, /*!< Sequentially visit 13 registers from base register */ 349 TIM_ADV_DMABurstBaseLen_Alt13 = 13u, /*!< Sequentially visit 14 registers from base register */ 350 TIM_ADV_DMABurstBaseLen_Alt14 = 14u, /*!< Sequentially visit 15 registers from base register */ 351 TIM_ADV_DMABurstBaseLen_Alt15 = 15u, /*!< Sequentially visit 16 registers from base register */ 352 TIM_ADV_DMABurstBaseLen_Alt16 = 16u, /*!< Sequentially visit 17 registers from base register */ 353 TIM_ADV_DMABurstBaseLen_Alt17 = 17u, /*!< Sequentially visit 18 registers from base register */ 354 } TIM_ADV_DMABurstBaseLen_Type; 355 356 /*! 357 * @brief TIM encoder direction. 358 */ 359 typedef enum 360 { 361 TIM_ADV_EncoderDirection_Forward = 0u, /*!< Encoder rotates in forward direction. */ 362 TIM_ADV_EncoderDirection_Backward = 1u, /*!< Encoder rotates in backward direction. */ 363 } TIM_ADV_EncoderDirection_Type; 364 365 /*! 366 * @brief TIM lock level. 367 */ 368 typedef enum 369 { 370 TIM_ADV_LockLevel_Disable = 0u, /*!< Unlock. */ 371 TIM_ADV_LockLevel_Alt0 = 1u, /*!< Lock level 1. */ 372 TIM_ADV_LockLevel_Alt1 = 2u, /*!< Lock level 2. */ 373 TIM_ADV_LockLevel_Alt2 = 3u, /*!< Lock level 3. */ 374 } TIM_ADV_LockLevel_Type; 375 376 /*! 377 * @brief This type of structure instance is used to keep the settings when calling the @ref TIM_ADV_Init() to initialize the TIM module time base unit. 378 */ 379 typedef struct 380 { 381 uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */ 382 uint32_t StepFreqHz; /*!< Step length value. Counter freq = ClockSourceFreqHz / (ClockSourceDiv+1). */ 383 uint32_t Period; /*!< Counter counting period length, from 0 to Period. */ 384 bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */ 385 TIM_ADV_PeriodMode_Type PeriodMode; /*!< Counter working period times. */ 386 TIM_ADV_CountMode_Type CountMode; /*!< Counter count direction. */ 387 } TIM_ADV_Init_Type; 388 389 /*! 390 * @brief This type of structure instance is used to setup the output compare feature when calling the @ref TIM_ADV_EnableOutputCompare() to enable the TIM module output compare channel. 391 */ 392 typedef struct 393 { 394 uint16_t ChannelValue; /*!< Value to be compared with counter. */ 395 bool EnableFastOutput; /*!< Enable fast response to the trigger input event. */ 396 bool EnablePreLoadChannelValue; /*!< Enable the preload of channel value. If enable, it will be updated in next period, otherwise immediately. */ 397 TIM_ADV_OutputCompareRefOut_Type RefOutMode; /*!< The reference output when counter matching the channel value. */ 398 bool ClearRefOutOnExtTrigger; /*!< External trigger high will clear the reference. */ 399 TIM_ADV_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ 400 TIM_ADV_PinPolarity_Type COMPPinPolarity; /*!< Set the complementary channel output. */ 401 } TIM_ADV_OutputCompareConf_Type; 402 403 /*! 404 * @brief This type of structure instance is used to setup the input capture feature when calling the @ref TIM_ADV_EnableInputCapture() to enable the TIM module input capture channel. 405 */ 406 typedef struct 407 { 408 TIM_ADV_InputCaptureInDiv_Type InDiv; /*!< The division of filtered input. */ 409 TIM_ADV_InputCaptureInFilter_Type InFilter; /*!< The filter sampling time for initial input. */ 410 TIM_ADV_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ 411 } TIM_ADV_InputCaptureConf_Type; 412 413 /*! 414 * @brief This type of structure instance is used to setup the dead time feature when calling the @ref TIM_ADV_EnableDeadArea() to enable the TIM module dead time area set. 415 * | DeadAreaCoef | Real Dead Area Time | 416 * | ------------ | --------------------------------------------------- | 417 * | 0xxxxxxx | DeadAreaCoef * DeadAreaStep | 418 * | 10xxxxxx | ( 64 + DeadAreaCoef[5:0] ) * ( 2 * DeadAreaStep ) | 419 * | 110xxxxx | ( 32 + DeadAreaCoef[4:0] ) * ( 8 * DeadAreaStep ） | 420 * | 111xxxxx | ( 32 + DeadAreaCoef[4:0] ) * ( 16 * DeadAreaStep ) | 421 */ 422 typedef struct 423 { 424 TIM_ADV_DeadAreaStep_Type StepFreqHz; /*!< Dead time area step set. */ 425 uint8_t DeadAreaCoef; /*!< The coefficient with bias to multiply with StepFreqHz to get the final dead area time. */ 426 } TIM_ADV_DeadAreaConf_Type; 427 428 /*! 429 * @brief This type of structure instance is used to setup the master mode configuration when calling the @ref TIM_ADV_EnableMasterMode(). 430 */ 431 typedef struct 432 { 433 TIM_ADV_MasterOut_Type Out; /*!< Master mode output selection. */ 434 bool EnableSync; /*!< Enable sychronize with slave timers. */ 435 } TIM_ADV_MasterModeConf_Type; 436 437 /*! 438 * @brief This type of structure instance is used to setup the slave mode configuration when calling the @ref TIM_ADV_EnableSlaveMode(). 439 */ 440 typedef struct 441 { 442 TIM_ADV_SlaveIn_Type In; /*!< Input trigger selection for slave timer. */ 443 TIM_ADV_SlaveResp_Type Resp; /*!< Slave timer counter response for its input trigger. */ 444 } TIM_ADV_SlaveModeConf_Type; 445 446 /*! 447 * @brief This type of structure instance is used to setup the external trigger input configuration when calling the @ref TIM_ADV_EnableExtTriggerIn(). 448 */ 449 typedef struct 450 { 451 TIM_ADV_ExtTriggerInDiv_Type InDiv; /*!< The division of filtered input. */ 452 TIM_ADV_ExtTriggerInFilter_Type InFilter; /*!< The filter sampling time for initial input. */ 453 TIM_ADV_ExtTriggerPinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ 454 } TIM_ADV_ExtTriggerInConf_Type; 455 456 /*! 457 * @brief This type of structure instance is used to setup the dma burst configuration when calling the @ref TIM_ADV_EnableDMABurst(). 458 */ 459 typedef struct 460 { 461 TIM_ADV_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */ 462 TIM_ADV_DMABurstBaseLen_Type Length; /*!< Length of sequential registers DMA burst visits. */ 463 } TIM_ADV_DMABurstConf_Type; 464 465 /*! 466 * @brief This type of structure instance is used to setup the idle state output when calling the @ref TIM_ADV_EnableIdleOut(). 467 */ 468 typedef struct 469 { 470 TIM_ADV_PinPolarity_Type PinPolarity; /*!< The output state of channel under idle mode. */ 471 TIM_ADV_PinPolarity_Type COMPPinPolarity; /*!< The output state of complementary channel under idle mode. */ 472 } TIM_ADV_IdleOut_Type; 473 474 /*! 475 * @brief This type of structure instance is used to setup the break in configuration when calling the @ref TIM_ADV_EnableBreakIn(). 476 */ 477 typedef struct 478 { 479 TIM_ADV_PinPolarity_Type PinPolarity; /*!< The active edge of the break in signal. */ 480 bool AutoSwitchOutput; /*!< If input signal is inactive, switch the output compare at next update. */ 481 bool DirectIdleOutput; /*!< If enable, output the set idle state directly. */ 482 } TIM_ADV_BreakIn_Type; 483 484 /*! 485 * @brief Set the timer's step for indicated TIM module. 486 * 487 * @param TIMx TIM_ADV instance. 488 * @param init Pointer to the initialization structure. See to @ref TIM_ADV_Init_Type. 489 * @return val 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz. 490 */ 491 bool TIM_ADV_Init(TIM_ADV_Type * TIMx, TIM_ADV_Init_Type * init); 492 493 /*! 494 * @brief Start counting. 495 * 496 * @param TIMx TIM_ADV instance. 497 * @return None. 498 */ 499 void TIM_ADV_Start(TIM_ADV_Type * TIMx); 500 501 /*! 502 * @brief Stop counting immediately. 503 * 504 * @param TIMx TIM_ADV instance. 505 * @return None. 506 */ 507 void TIM_ADV_Stop(TIM_ADV_Type * TIMx); 508 509 /*! 510 * @brief Get the indicated TIMx Counter value. 511 * 512 * @param TIMx TIM_ADV_Type instance. 513 * @return The current value of the counter register. 514 */ 515 uint32_t TIM_ADV_GetCounterValue(TIM_ADV_Type * TIMx); 516 517 /*! 518 * @brief Clear the indicated TIMx Counter. 519 * 520 * @param TIMx TIM_ADV_Type instance. 521 * @return None. 522 */ 523 void TIM_ADV_ClearCounterValue(TIM_ADV_Type * TIMx); 524 525 /*! 526 * @brief Enable the TIM_ADV interrupts. 527 * 528 * @param TIMx TIM_ADV_Type instance. 529 * @param interrupts Interrupts to be enabled.See to @ref TIM_ADV_INT. 530 * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs. 531 * @return None. 532 */ 533 void TIM_ADV_EnableInterrupts(TIM_ADV_Type * TIMx, uint32_t interrupts, bool enable); 534 535 /*! 536 * @brief Enable the TIM_ADV DMAs. 537 * 538 * @param TIMx TIM_ADV_Type instance. 539 * @param dmas DMA masks to be enabled. See to @ref TIM_ADV_DMA. 540 * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs. 541 * @return None. 542 */ 543 void TIM_ADV_EnableDMA(TIM_ADV_Type * TIMx, uint32_t dmas, bool enable); 544 545 /*! 546 * @brief Software trigger events to call interrupts or DMAs. 547 * 548 * Can simultaneously trigger multiple events. 549 * 550 * @param TIMx TIM_ADV instance. See to @ref TIM_ADV_SWTRG. 551 * @param swtrgs Trigger the events to generate interrupts. 552 */ 553 void TIM_ADV_DoSwTrigger(TIM_ADV_Type * TIMx, uint32_t swtrgs); 554 555 /*! 556 * @brief Get the status of the indicated timer. 557 * 558 * @param TIMx TIM_ADV_Type instance. 559 * @return Interrupt status flags. See to @ref TIM_ADV_INT_STATUS. 560 */ 561 uint32_t TIM_ADV_GetInterruptStatus(TIM_ADV_Type * TIMx); 562 563 /*! 564 * @brief Clear the status of indicated interrupt. 565 * 566 * @param TIMx TIM_ADV_Type instance. 567 * @param status The required clear flag type. See to @ref TIM_ADV_INT_STATUS. 568 * @return None. 569 */ 570 void TIM_ADV_ClearInterruptStatus(TIM_ADV_Type * TIMx, uint32_t status); 571 572 /*! 573 * @brief Set up the output compare feature of indicated timer channel. 574 * 575 * If need to change the IO mode of the working channel, channel must be disabled first, then modify. 576 * 577 * @param TIMx TIM_ADV_Type instance. 578 * @param channel Output channel instance. See to @ref TIM_ADV_CHANNEL_SELECTION. 579 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_OutputCompareConf_Type. 580 * @return None. 581 */ 582 void TIM_ADV_EnableOutputCompare(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_OutputCompareConf_Type * conf); 583 584 /*! 585 * @brief Enable the TIM_ADV channel output for pulse generation. 586 * 587 * @param TIMx TIM_ADV_Type instance. 588 * @param enable 'true' to enable the channel output, 'false' to disable the channel output. 589 * @return None. 590 */ 591 void TIM_ADV_EnableOutputCompareSwitch(TIM_ADV_Type * TIMx, bool enable); 592 593 /*! 594 * @brief Enable the input capture feature of indicated timer channel. 595 * 596 * If need to change the IO mode of the working channel, channel must be disabled first, then modify. 597 * 598 * @param TIMx TIM_ADV_Type instance. 599 * @param channel Input channel instance. See to @ref TIM_ADV_CHANNEL_SELECTION. 600 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_InputCaptureConf_Type. 601 * @return None. 602 */ 603 void TIM_ADV_EnableInputCapture(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_InputCaptureConf_Type * conf); 604 605 /*! 606 * @brief Get the value of the indicated timer channel. 607 * 608 * When capture event happens, counter value will be kept in its indicated channel. 609 * 610 * @param TIMx TIM_ADV_Type instance. 611 * @param channel Channel instance to get the value. See to @ref TIM_ADV_CHANNEL_SELECTION. 612 * @return Value of the indiacted timer channel. 613 */ 614 uint16_t TIM_ADV_GetChannelValue(TIM_ADV_Type * TIMx, uint32_t channel); 615 616 /*! 617 * @brief Put the value into the indicated timer channel. 618 * 619 * When in output compare, channel value would be the compared with counter value. 620 * 621 * @param TIMx TIM_ADV_Type instance. 622 * @param channel Channel instance to put the value. See to @ref TIM_ADV_CHANNEL_SELECTION. 623 * @param value The value to be set in the indicated timer channel. 624 * @return None. 625 */ 626 void TIM_ADV_PutChannelValue(TIM_ADV_Type * TIMx, uint32_t channel, uint16_t value); 627 628 /*! 629 * @brief Enable the dead area of the indicated timer. 630 * 631 * @param TIMx TIM_ADV_Type instance. 632 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_DeadAreaConf_Type. 633 * @return None. 634 */ 635 void TIM_ADV_EnableDeadArea(TIM_ADV_Type * TIMx, TIM_ADV_DeadAreaConf_Type * conf); 636 637 /*! 638 * @brief Enable the master mode of the indicated timer. 639 * 640 * Master mode transfer the timer signal to other timers. 641 * 642 * @param TIMx TIM_ADV_Type instance. 643 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_MasterModeConf_Type. 644 * @return None. 645 */ 646 void TIM_ADV_EnableMasterMode(TIM_ADV_Type * TIMx, TIM_ADV_MasterModeConf_Type * conf); 647 648 /*! 649 * @brief Enable the slave mode of the indicated timer. 650 * 651 * Slave mode can control the working state of counter. 652 * 653 * @param TIMx TIM_ADV_Type instance. 654 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_SlaveModeConf_Type. 655 * @return None. 656 */ 657 void TIM_ADV_EnableSlaveMode(TIM_ADV_Type * TIMx, TIM_ADV_SlaveModeConf_Type * conf); 658 659 /*! 660 * @brief Enable the external trigger input of the indicated counter. 661 * 662 * External trigger signal will trigger counter do addition. 663 * Its div and filter along with the counter StepFreqHz will affect. 664 * 665 * @param TIMx TIM_ADV_Type instance. 666 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_ExtTriggerInConf_Type. 667 * @return None. 668 */ 669 void TIM_ADV_EnableExtTriggerIn(TIM_ADV_Type * TIMx, TIM_ADV_ExtTriggerInConf_Type * conf); 670 671 /*! 672 * @brief Enable the dma burst transfer of the indicated timer. 673 * 674 * @param TIMx TIM_ADV_Type instance. 675 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_DMABurstConf_Type. 676 * @return Address of DMA Burst transfer base register address. 677 */ 678 uint32_t TIM_ADV_EnableDMABurst(TIM_ADV_Type * TIMx, TIM_ADV_DMABurstConf_Type * conf); 679 680 /*! 681 * @brief Get the encoder rotating direction and the counted encoder pulse times. 682 * 683 * @param TIMx TIM_ADV_Type instance. 684 * @param value The counter value for pulse times. 685 * @return Encoder rotating direction. See to @ref TIM_ADV_EncoderDirection_Type. 686 */ 687 TIM_ADV_EncoderDirection_Type TIM_ADV_GetEncoder(TIM_ADV_Type * TIMx, uint32_t * value); 688 689 /*! 690 * @brief Set the indicated TIMx repetition counter value. 691 * 692 * @param TIMx TIM_ADV_Type instance. 693 * @param value The repetition value to be set. 694 * @return The current value of the counter register. 695 */ 696 void TIM_ADV_SetRepCounter(TIM_ADV_Type * TIMx, uint8_t value); 697 698 /*! 699 * @brief Get the indicated TIMx Counter value. 700 * 701 * Real repetition's times number, meaning left repetition period times to run. 702 * 703 * @param TIMx TIM_ADV_Type instance. 704 * @return The current value of the counter register. 705 */ 706 uint8_t TIM_ADV_GetRepCounterValue(TIM_ADV_Type * TIMx); 707 708 /*! 709 * @brief Set the channel idle state output when switch off the output compare. 710 * 711 * @param TIMx TIM_ADV_Type instance. 712 * @param channel Channel instance to set the idle state output. See to @ref TIM_ADV_CHANNEL_SELECTION. 713 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_IdleOut_Type. 714 * @return None. 715 */ 716 void TIM_ADV_EnableIdleOut(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_IdleOut_Type * conf); 717 718 /*! 719 * @brief Set the lock level for protecting the timer config setting. 720 * 721 * @param TIMx TIM_ADV_Type instance. 722 * @param lock Lock level to be set for protecting Timer set. See to @ref TIM_ADV_LockLevel_Type. 723 * @return None. 724 */ 725 void TIM_ADV_EnableLock(TIM_ADV_Type * TIMx, TIM_ADV_LockLevel_Type lock); 726 727 /*! 728 * @brief Set the break input of the timer. 729 * 730 * @param TIMx TIM_ADV_Type instance. 731 * @param conf Pointer to the configuration structure. See to @ref TIM_ADV_BreakIn_Type. 732 * @return None. 733 */ 734 void TIM_ADV_EnableBreakIn(TIM_ADV_Type * TIMx, TIM_ADV_BreakIn_Type * conf); 735 736 /*! 737 * @brief Set the PWM shift of the indicated channel. 738 * 739 * @param TIMx TIM_ADV_Type instance. 740 * @param channel Channel instance to set the pwm shift. See to @ref TIM_ADV_CHANNEL_SELECTION. 741 * @param value The counter time when need pwm output shift. If val equals the channel value, disable the shift. 742 * @return None. 743 */ 744 void TIM_ADV_EnablePWMShift(TIM_ADV_Type * TIMx, uint32_t channel, uint16_t value); 745 746 /*! 747 *@} 748 */ 749 #endif /* __HAL_TIM_ADV_H__ */ 750 751