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Searched refs:TPR (Results 1 – 25 of 382) sorted by relevance

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/bsp/ti/c28x/libraries/tms320f28379d/common/source/
A DF2837xD_CpuTimers.c76 CpuTimer0Regs.TPR.all = 0; in InitCpuTimers()
109 CpuTimer1Regs.TPR.all = 0; in InitCpuTimers()
111 CpuTimer2Regs.TPR.all = 0; in InitCpuTimers()
158 Timer->RegsAddr->TPR.all = 0; in ConfigCpuTimer()
A DF2837xD_SysCtrl.c740 t1TPR = CpuTimer1Regs.TPR.all; in InitSysPll()
746 t2TPR = CpuTimer2Regs.TPR.all; in InitSysPll()
755 CpuTimer1Regs.TPR.bit.TDDR = 0x0; // sysclock divider in InitSysPll()
783 CpuTimer2Regs.TPR.bit.TDDR = 0x0; // sysclock divider in InitSysPll()
815 CpuTimer1Regs.TPR.all = t1TPR; in InitSysPll()
821 CpuTimer2Regs.TPR.all = t2TPR; in InitSysPll()
938 t2TPR = CpuTimer2Regs.TPR.all; in InitAuxPll()
950 CpuTimer2Regs.TPR.all = 0; in InitAuxPll()
1105 CpuTimer2Regs.TPR.all = t2TPR; in InitAuxPll()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_usart.c411 USARTx->TPR |= USART_TIMEOUT_ON; in USART_IntConfig()
415 USARTx->TPR &= USART_TIMEOUT_OFF; in USART_IntConfig()
616 USARTx->TPR = (USARTx->TPR & TPR_TG_Mask) | (USART_GuardTime << 0x08); in USART_SetGuardTime()
667 USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut; in USART_SetTimeOutValue()
669 USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut | USART_RXTOEN_ON; in USART_SetTimeOutValue()
1053 USARTx->TPR |= USART_TIMEOUT_ON;
1057 USARTx->TPR &= USART_TIMEOUT_OFF;
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_usart.c522 USARTx->TPR = (USARTx->TPR & TPR_TG_Mask) | (USART_GuardTime << 0x08); in USART_SetGuardTime()
562 USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut | USART_RXTOEN_ON; in USART_SetTimeOutValue()
/bsp/ti/c28x/libraries/tms320f28379d/headers/include/
A DF2837xD_cputimer.h116 …union TPR_REG TPR; // CPU-Timer, Prescale Regi… member
/bsp/at91/at91sam9260/drivers/
A Dboard.c164 volatile rt_uint32_t TPR; member
A Dusart.c41 volatile rt_uint32_t TPR; member
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/
A Dht32f1xxxx_01.h408 …__IO uint32_t TPR; /*!< 0x020 Timing Parameter Register … member
422 …__IO uint32_t TPR; /*!< 0x014 Timing Parameter Register …
/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/
A Dcore_cm3.h621 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
A Dcore_cm4.h651 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/
A Dcore_cm3.h452 …__IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register … member
/bsp/smartfusion2/CMSIS/
A Dcore_cm3.h427 …__IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register … member
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/
A Dcore_cm3.h421 …__IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register … member
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/CMSIS/
A Dcore_cm3.h421 …__IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register … member
/bsp/efm32/Libraries/CMSIS/Include/
A Dcore_cm3.h636 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/
A Dcore_cm3.h636 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/
A Dcore_cm3.h651 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
A Dcore_sc300.h622 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
/bsp/CME_M7/CMSIS/CMSIS/Include/
A Dcore_sc300.h622 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
A Dcore_cm3.h651 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
/bsp/samd21/sam_d2x_asflib/CMSIS/Include/
A Dcore_cm3.h671 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
A Dcore_sc300.h651 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/
A Dcore_cm3.h651 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
/bsp/mm32l07x/Libraries/CMSIS/CORE/
A Dcore_cm3.h651 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
A Dcore_sc300.h622 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member

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