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Searched refs:TR (Results 1 – 25 of 84) sorted by relevance

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/bsp/nuvoton/libraries/m460/rtt_port/emac/
A DsynopGMAC_network_interface.c45 TR("GMAC wokeup due to Magic Pkt Received\n"); in synopGMAC_powerup_mac()
47 TR("GMAC wokeup due to Wakeup Frame Received\n"); in synopGMAC_powerup_mac()
62 TR("Put the GMAC to power down mode..\n"); in synopGMAC_powerdown_mac()
132 TR("GMAC wokeup due to Magic Pkt Received\n");
134 TR("GMAC wokeup due to Wakeup Frame Received\n");
431 TR("Error in Status %08x\n", status); in synop_handle_transmit_over()
496 TR("Checksum Offloading will be done now\n"); in synop_handle_received_data()
500 TR("Extended Status present\n"); in synop_handle_received_data()
504 TR("(EXTSTS)Error in IP header error\n"); in synop_handle_received_data()
513 TR("(EXTSTS) Error in EP payload\n"); in synop_handle_received_data()
[all …]
A DsynopGMAC_plat.c25 …TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOff… in synopGMACReadReg()
37 …TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32) RegBase, RegOf… in synopGMACWriteReg()
55 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data); in synopGMACSetBits()
68 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data); in synopGMACClearBits()
A DsynopGMAC_plat.h30 #undef TR
31 #define TR(fmt, args...) rt_kprintf("SynopGMAC: " fmt, ##args) macro
33 #define TR(fmt, args...) /* not debugging: nothing */ macro
A DsynopGMAC_Dev.c100 TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); in synopGMAC_read_phy_reg()
142 TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); in synopGMAC_write_phy_reg()
181 TR("The data read from %08x is %08x\n", (gmacdev->MacBase + GmacVersion), data); in synopGMAC_read_version()
205 TR("DATA after Reset = %08x\n", data); in synopGMAC_reset()
508 TR("strips status : %u\n", status & GmacPadCrcStrip); in synopGMAC_pad_crc_strip_disable()
1250 TR("At line %d\n", __LINE__); in synopGMAC_init_tx_rx_desc_queue()
1535 …TR("%02d %08x %08x %08x %08x %08x\n", txover, (u32)txdesc, txdesc->status, txdesc->length, txdesc-… in synopGMAC_get_tx_qptr()
1671 …TR("%02d %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc-… in synopGMAC_set_rx_qptr()
2722 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_addend_update()
2754 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_timestamp_update()
[all …]
/bsp/nuvoton/libraries/ma35/rtt_port/gmac/
A DsynopGMAC_network_interface.c45 TR("GMAC wokeup due to Magic Pkt Received\n"); in synopGMAC_powerup_mac()
47 TR("GMAC wokeup due to Wakeup Frame Received\n"); in synopGMAC_powerup_mac()
62 TR("Put the GMAC to power down mode..\n"); in synopGMAC_powerdown_mac()
132 TR("GMAC wokeup due to Magic Pkt Received\n");
134 TR("GMAC wokeup due to Wakeup Frame Received\n");
431 TR("Error in Status %08x\n", status); in synop_handle_transmit_over()
496 TR("Checksum Offloading will be done now\n"); in synop_handle_received_data()
500 TR("Extended Status present\n"); in synop_handle_received_data()
504 TR("(EXTSTS)Error in IP header error\n"); in synop_handle_received_data()
513 TR("(EXTSTS) Error in EP payload\n"); in synop_handle_received_data()
[all …]
A DsynopGMAC_plat.c25 …TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOff… in synopGMACReadReg()
36 …TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32) RegBase, RegOf… in synopGMACWriteReg()
51 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data); in synopGMACSetBits()
64 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data); in synopGMACClearBits()
A DsynopGMAC_plat.h31 #undef TR
32 #define TR(fmt, args...) rt_kprintf("SynopGMAC: " fmt, ##args) macro
34 #define TR(fmt, args...) /* not debugging: nothing */ macro
A DsynopGMAC_Dev.c100 TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); in synopGMAC_read_phy_reg()
142 TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); in synopGMAC_write_phy_reg()
181 TR("The data read from %08x is %08x\n", (gmacdev->MacBase + GmacVersion), data); in synopGMAC_read_version()
205 TR("DATA after Reset = %08x\n", data); in synopGMAC_reset()
508 TR("strips status : %u\n", status & GmacPadCrcStrip); in synopGMAC_pad_crc_strip_disable()
1250 TR("At line %d\n", __LINE__); in synopGMAC_init_tx_rx_desc_queue()
1535 …TR("%02d %08x %08x %08x %08x %08x\n", txover, (u32)txdesc, txdesc->status, txdesc->length, txdesc-… in synopGMAC_get_tx_qptr()
1671 …TR("%02d %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc-… in synopGMAC_set_rx_qptr()
2722 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_addend_update()
2754 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_timestamp_update()
[all …]
/bsp/loongson/ls1cdev/drivers/net/
A DsynopGMAC_plat.h87 #define TR(fmt, args...) //rt_kprintf(fmt, ##args) macro
152 …TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOff… in synopGMACReadReg()
175 …TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOff… in synopGMACWriteReg()
201 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data ); in synopGMACSetBits()
222 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data ); in synopGMACClearBits()
A DsynopGMAC_Dev.c81 TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); in synopGMAC_read_phy_reg()
186 TR("DATA after Reset = %08x\n",data); in synopGMAC_reset()
1027 TR("\n===phy FULLDUPLEX MODE\n"); //sw: debug in synopGMAC_mac_init()
1080 TR("\n===phy HALFDUPLEX MODE\n"); //sw: debug in synopGMAC_mac_init()
1368 TR("At line %d\n",__LINE__); in synopGMAC_init_tx_rx_desc_queue()
1930 TR("set tx qptr: desc empty!\n"); in synopGMAC_set_tx_qptr()
2360 TR("DMA status reg = 0x%x before cleared!\n",data); in synopGMAC_clear_interrupt()
2364 TR("DMA status reg = 0x%x after cleared!\n",data); in synopGMAC_clear_interrupt()
3513 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_addend_update()
3542 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_timestamp_update()
[all …]
A DsynopGMAC.c653 TR("phy reg25 is %0x \n", data); in init_phy()
665 TR("phy reg16 is 0x%0x \n", data); in init_phy()
861 TR("%s::Transmitter stopped sending the packets\n", __FUNCTION__); in eth_rx_irq()
869 TR("%s::Transmission Resumed\n", __FUNCTION__); in eth_rx_irq()
/bsp/loongson/ls2kdev/drivers/net/
A DsynopGMAC_plat.h85 #define TR(fmt, args...) //rt_kprintf(fmt, ##args) macro
145 …TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOff… in synopGMACReadReg()
166 …TR("%s RegBase = 0x%p RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffse… in synopGMACWriteReg()
191 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data ); in synopGMACSetBits()
212 TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data ); in synopGMACClearBits()
A DsynopGMAC_Dev.c88 TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); in synopGMAC_read_phy_reg()
203 TR("DATA after Reset = %08x\n", data); in synopGMAC_reset()
1049 TR("\n===phy FULLDUPLEX MODE\n"); //sw: debug in synopGMAC_mac_init()
1112 TR("\n===phy HALFDUPLEX MODE\n"); //sw: debug in synopGMAC_mac_init()
1417 TR("At line %d\n", __LINE__); in synopGMAC_init_tx_rx_desc_queue()
1998 TR("set tx qptr: desc empty!\n"); in synopGMAC_set_tx_qptr()
2441 TR("DMA status reg = 0x%x before cleared!\n", data); in synopGMAC_clear_interrupt()
2445 TR("DMA status reg = 0x%x after cleared!\n", data); in synopGMAC_clear_interrupt()
3579 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_addend_update()
3610 TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); in synopGMAC_TS_timestamp_update()
[all …]
A DsynopGMAC.c690 TR("phy reg25 is %0x \n", data); in init_phy()
702 TR("phy reg16 is 0x%0x \n", data); in init_phy()
898 TR("%s::Transmitter stopped sending the packets\n", __FUNCTION__); in eth_rx_irq()
906 TR("%s::Transmission Resumed\n", __FUNCTION__); in eth_rx_irq()
/bsp/synwit/libraries/SWM341_CSL/SWM341_StdPeriph_Driver/
A DSWM341_i2c.c176 return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1; in I2C_Start()
186 return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1; in I2C_IsAck()
231 return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1; in I2C_Write()
250 I2Cx->TR = ((ack ? 0 : 1) << I2C_TR_TXACK_Pos); in I2C_Read()
/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/
A Dlpt.c217 M0P_LPTIMER->CR_f.TR = TRUE; in Lpt_Run()
235 M0P_LPTIMER->CR_f.TR = FALSE; in Lpt_Stop()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_rtc.h1083 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1100 return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); in LL_RTC_TIME_GetFormat()
1116 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1135 return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); in LL_RTC_TIME_GetHour()
1151 MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), in LL_RTC_TIME_SetMinute()
1170 return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); in LL_RTC_TIME_GetMinute()
1186 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
1205 return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); in LL_RTC_TIME_GetSecond()
1237 …MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RT… in LL_RTC_TIME_Config()
1261 …temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU… in LL_RTC_TIME_Get()
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/
A Dtae32f53xx_ll_adc.c366 CLEAR_BIT(Instance->TR[0], ADC_TR0_HT0 | ADC_TR0_LT0); in LL_ADC_DeInit()
370 CLEAR_BIT(Instance->TR[1], ADC_TR1_HT1 | ADC_TR1_LT1); in LL_ADC_DeInit()
374 CLEAR_BIT(Instance->TR[2], ADC_TR2_HT2 | ADC_TR2_LT2); in LL_ADC_DeInit()
825 MODIFY_REG(Instance->TR[AnalogWDGConfig->WatchdogNumber], in LL_ADC_AnalogWDGConfig()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_mu.c65 base->TR[regIndex] = msg; in MU_SendMsg()
A Dfsl_mu.h173 base->TR[regIndex] = msg; in MU_SendMsgNonBlocking()
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/
A Dft32f0xx_rtc.c73 RTC->TR = (uint32_t)0x00000000; in RTC_DeInit()
492 RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); in RTC_SetTime()
555 tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); in RTC_GetTime()
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/
A Dhk32f0xx_rtc.c303 RTC->TR = (uint32_t)0x00000000; in RTC_DeInit()
739 RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); in RTC_SetTime()
802 tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); in RTC_GetTime()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_can.c300 CANx->TR = u8TestMask; in CAN_EnterTestMode()
314 CANx->TR &= ~(CAN_MODE_LBACK | CAN_MODE_SILENT | CAN_MODE_BASIC | CAN_MODE_TX_RECESSIVE); in CAN_LeaveTestMode()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_hal_rtc.c390 hrtc->Instance->TR = 0x00000000U; in HAL_RTC_DeInit()
811 hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); in HAL_RTC_SetTime()
884 tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); in HAL_RTC_GetTime()
/bsp/at91/at91sam9260/debug_scripts/
A Dat91sam9260.gdb199 …# psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; # Set Refresh Timer 390 for 25MHz (TR= 1…

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