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Searched refs:TSENS_SYNCBUSY_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/microchip/samc21/bsp/hri/
A Dhri_tsens_c21.h433 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_set_CTRLA_RUNSTDBY_bit()
453 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_write_CTRLA_RUNSTDBY_bit()
461 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_clear_CTRLA_RUNSTDBY_bit()
469 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_toggle_CTRLA_RUNSTDBY_bit()
477 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_set_CTRLA_reg()
484 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_get_CTRLA_reg()
494 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_write_CTRLA_reg()
502 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_clear_CTRLA_reg()
510 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_toggle_CTRLA_reg()
516 hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); in hri_tsens_read_CTRLA_reg()
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dtsens.h264 #define TSENS_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (TSENS_SYNCBUSY) MASK Register */ macro

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