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Searched refs:TXFTLR (Results 1 – 8 of 8) sorted by relevance

/bsp/ck802/libraries/common/spi/
A Ddw_spi.h127 __IOM uint32_t TXFTLR; /* Offset: 0x018 (R/W) Transmit FIFO Threshold Level */ member
A Ddw_spi.c971 addr->TXFTLR = DW_SPI_TXFIFO_LV; in csi_spi_send()
1002 addr->TXFTLR = DW_SPI_TXFIFO_LV; in csi_spi_send()
1190 addr->TXFTLR = DW_SPI_TXFIFO_LV; in csi_spi_transfer()
/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_spi.c424 SPI->TXFTLR = 0; in SPI_MasterInit()
612 SPI->TXFTLR = SPIM_FIFO_TX_LEVEL; in SPI_Transfer()
/bsp/airm2m/air105/libraries/HAL_Driver/Inc/
A Dair105.h321 __IO uint32_t TXFTLR; member
/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/
A Drk2108.h531 __IO uint32_t TXFTLR; /* Address Offset: 0x0014 */ member
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G074.h11497 …__IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register … member
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h25378 …__IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register … member
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h25378 …__IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register … member

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