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/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/
A Dht32f5xxxx_exti.h143 #define IS_EXTI_INT_TYPE(TYPE) ((TYPE == EXTI_LOW_LEVEL) || \ argument
144 (TYPE == EXTI_HIGH_LEVEL) || \
145 (TYPE == EXTI_NEGATIVE_EDGE) || \
146 (TYPE == EXTI_POSITIVE_EDGE) || \
147 (TYPE == EXTI_BOTH_EDGE))
155 #define IS_EXTI_DEBOUNCE_TYPE(TYPE) ((TYPE == EXTI_DEBOUNCE_DISABLE) || \ argument
156 (TYPE == EXTI_DEBOUNCE_ENABLE))
171 #define IS_EXTI_DEBOUNCE_COUNTER_PRESCALER(TYPE) ((TYPE == EXTI_DBCNTPRE_DIV1) || \ argument
178 (TYPE == EXTI_DBCNTPRE_DIV128))
205 #define IS_EXTI_WAKEUP_TYPE(TYPE) ((TYPE == EXTI_WAKEUP_HIGH_LEVEL) || \ argument
[all …]
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/
A Dht32f1xxxx_exti.h114 #define IS_EXTI_INT_TYPE(TYPE) ((TYPE == EXTI_LOW_LEVEL) || \ argument
115 (TYPE == EXTI_HIGH_LEVEL) || \
116 (TYPE == EXTI_NEGATIVE_EDGE) || \
117 (TYPE == EXTI_POSITIVE_EDGE) || \
118 (TYPE == EXTI_BOTH_EDGE))
126 #define IS_EXTI_DEBOUNCE_TYPE(TYPE) ((TYPE == EXTI_DEBOUNCE_DISABLE) || \ argument
127 (TYPE == EXTI_DEBOUNCE_ENABLE))
153 #define IS_EXTI_WAKEUP_TYPE(TYPE) ((TYPE == EXTI_WAKEUP_HIGH_LEVEL) || \ argument
154 (TYPE == EXTI_WAKEUP_LOW_LEVEL))
A Dht32f2xxxx_csif.h106 #define IS_CSIF_VSYNC_TYPE(TYPE) ((TYPE == CSIF_VSYNCTYPE_PULSE) || \ argument
107 (TYPE == CSIF_VSYNCTYPE_OVERLAP))
113 #define IS_CSIF_HSYNC_TYPE(TYPE) ((TYPE == CSIF_HSYNCTYPE_CONTINUOUS) || \ argument
114 (TYPE == CSIF_HSYNCTYPE_DISCONTINUOUS))
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_cortex.h310 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
311 ((TYPE) == MPU_TEX_LEVEL1) || \
312 ((TYPE) == MPU_TEX_LEVEL2))
314 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
315 ((TYPE) == MPU_REGION_PRIV_RW) || \
316 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
317 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
318 ((TYPE) == MPU_REGION_PRIV_RO) || \
319 ((TYPE) == MPU_REGION_PRIV_RO_URO))
A Dstm32l1xx_hal_rtc.h270 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ argument
271 ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_cmcc_d51.h67 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; in hri_cmcc_get_TYPE_GCLK_bit()
72 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; in hri_cmcc_get_TYPE_RRP_bit()
77 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; in hri_cmcc_get_TYPE_LCKDOWN_bit()
82 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; in hri_cmcc_get_TYPE_WAYNUM_bf()
87 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; in hri_cmcc_read_TYPE_WAYNUM_bf()
92 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; in hri_cmcc_get_TYPE_CSIZE_bf()
97 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; in hri_cmcc_read_TYPE_CSIZE_bf()
102 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; in hri_cmcc_get_TYPE_CLSIZE_bf()
107 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; in hri_cmcc_read_TYPE_CLSIZE_bf()
113 tmp = ((Cmcc *)hw)->TYPE.reg; in hri_cmcc_get_TYPE_reg()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_cmcc_d51.h67 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; in hri_cmcc_get_TYPE_GCLK_bit()
72 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; in hri_cmcc_get_TYPE_RRP_bit()
77 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; in hri_cmcc_get_TYPE_LCKDOWN_bit()
82 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; in hri_cmcc_get_TYPE_WAYNUM_bf()
87 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; in hri_cmcc_read_TYPE_WAYNUM_bf()
92 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; in hri_cmcc_get_TYPE_CSIZE_bf()
97 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; in hri_cmcc_read_TYPE_CSIZE_bf()
102 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; in hri_cmcc_get_TYPE_CLSIZE_bf()
107 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; in hri_cmcc_read_TYPE_CLSIZE_bf()
113 tmp = ((Cmcc *)hw)->TYPE.reg; in hri_cmcc_get_TYPE_reg()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_cmcc_e54.h67 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; in hri_cmcc_get_TYPE_GCLK_bit()
72 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; in hri_cmcc_get_TYPE_RRP_bit()
77 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; in hri_cmcc_get_TYPE_LCKDOWN_bit()
82 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; in hri_cmcc_get_TYPE_WAYNUM_bf()
87 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; in hri_cmcc_read_TYPE_WAYNUM_bf()
92 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; in hri_cmcc_get_TYPE_CSIZE_bf()
97 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; in hri_cmcc_read_TYPE_CSIZE_bf()
102 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; in hri_cmcc_get_TYPE_CLSIZE_bf()
107 return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; in hri_cmcc_read_TYPE_CLSIZE_bf()
113 tmp = ((Cmcc *)hw)->TYPE.reg; in hri_cmcc_get_TYPE_reg()
[all …]
/bsp/microchip/samc21/bsp/hri/
A Dhri_mpu_c21.h61 return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_SEPARATE) >> 0; in hri_mpu_get_TYPE_SEPARATE_bit()
66 return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION(mask)) >> 8; in hri_mpu_get_TYPE_DREGION_bf()
71 return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION_Msk) >> 8; in hri_mpu_read_TYPE_DREGION_bf()
76 return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION(mask)) >> 16; in hri_mpu_get_TYPE_IREGION_bf()
81 return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION_Msk) >> 16; in hri_mpu_read_TYPE_IREGION_bf()
87 tmp = ((Mpu *)hw)->TYPE.reg; in hri_mpu_get_TYPE_reg()
94 return ((Mpu *)hw)->TYPE.reg; in hri_mpu_read_TYPE_reg()
/bsp/cvitek/c906_little/board/
A Driscv-virt.h17 #define CONS(NUM, TYPE)NUM argument
19 #define CONS(NUM, TYPE)NUM##TYPE argument
/bsp/synopsys/boards/
A Dlinker_template_mw.ld72 *(TYPE text)
90 *(TYPE lit)
121 *(TYPE data)
139 *(TYPE bss)
/bsp/ti/c28x/tms320f28379d/cmd/
A D2837x_RAM_lnk_cpu1.cmd37 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
71 GETBUFFER : TYPE = DSECT
72 GETWRITEIDX : TYPE = DSECT
73 PUTREADIDX : TYPE = DSECT
A D2837x_FLASH_lnk_cpu1.cmd96 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
108 GETBUFFER : TYPE = DSECT
109 GETWRITEIDX : TYPE = DSECT
110 PUTREADIDX : TYPE = DSECT
/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Daw_common.h7 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) argument
/bsp/stm32/libraries/HAL_Drivers/drivers/
A Ddrv_can.h39 #define BAUD_DATA(TYPE,NO) ((can_baud_rate_tab[NO].config_data & TYPE##MASK)) argument
/bsp/bf533/vdsp/
A Dbf533_sdram_64M.ldf188 MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
189 MEM_L1_CODE_CACHE { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }
190 MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA0FFFF) WIDTH(8) }
191 MEM_L1_DATA_B_CACHE { TYPE(RAM) START(0xFF904000) END(0xFF907FFF) WIDTH(8) }
192 MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF903FFF) WIDTH(8) }
193 MEM_L1_DATA_A_CACHE { TYPE(RAM) START(0xFF804000) END(0xFF807FFF) WIDTH(8) }
194 MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) }
195 MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) }
196 MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) }
197 MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) }
[all …]
A Dbf533_ram.ldf182 MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
183 MEM_L1_CODE_CACHE { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }
184 MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA0FFFF) WIDTH(8) }
185 MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }
186 MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }
187 MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) }
188 MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) }
189 MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) }
190 MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) }
/bsp/allwinner/libraries/sunxi-hal/hal/source/sound/component/aw-alsa-lib/
A Dpcm_softvol.c159 #define CONVERT_AREA(TYPE, swap) do { \ argument
161 TYPE *src, *dst; \
167 src_step = snd_pcm_channel_area_step(src_area) / sizeof(TYPE); \
168 dst_step = snd_pcm_channel_area_step(dst_area) / sizeof(TYPE); \
184 *dst = (TYPE) MULTI_DIV_##TYPE(*src, vol_scale, swap); \
/bsp/efm32/Libraries/emlib/src/
A Dem_mpu.c92 EFM_ASSERT(init->regionNo < ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> in MPU_ConfigureRegion()
/bsp/nxp/lpc/lpc54608-LPCXpresso/drivers/
A Ddrt_mpu.c30 …MPU_PRINT("\nnumber of regions: %d\n", (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos); in rt_hw_mpu_init()
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_adc12_drv.h23 #define ADC12_IS_SIGNAL_TYPE_INVALID(TYPE) (TYPE > (uint32_t)adc12_sample_signal_count) argument
/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/
A Dn32g4fr_rtc.h489 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPUL… argument
/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/
A Dn32g45x_rtc.h489 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPUL… argument
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/
A Dn32wb452_rtc.h489 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPUL… argument
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/
A Dn32g45x_rtc.h489 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPUL… argument

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