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Searched refs:TypeExtField (Results 1 – 25 of 49) sorted by relevance

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/bsp/stm32/stm32h750-artpi/board/port/
A Ddrv_mpu.c29 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; in mpu_init()
45 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; in mpu_init()
63 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; in mpu_init()
79 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; in mpu_init()
/bsp/stm32/stm32h730-esphosted-evb/board/
A Dboard.c81 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; in MPU_Config()
94 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; in MPU_Config()
107 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; in MPU_Config()
120 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; in MPU_Config()
133 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; in MPU_Config()
146 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; in MPU_Config()
/bsp/airm2m/air105/libraries/HAL_Driver/Inc/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/microchip/samc21/bsp/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/microchip/samd51-seeed-wio-terminal/bsp/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/microchip/saml10/bsp/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/microchip/same70/bsp/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/stm32/libraries/HAL_Drivers/CMSIS/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/microchip/same54/bsp/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/microchip/samd51-adafruit-metro-m4/bsp/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
121 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
124 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
124 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
124 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
124 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/tae32f5300/Libraries/CMSIS/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
124 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
124 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…
/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dmpu_armv7.h88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ argument
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBuffe… argument
124 …ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCachea…

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