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/bsp/rm48x50/HALCoGen/include/
A Desm.h34 #define esmGROUP1 0U
637 esmSelfTest_Passed = 0U,
658 | (0U << 30U)\
659 | (0U << 29U)\
688 | (0U)
720 | (0U)
752 | (0U)
754 #define ESM_KEY_CONFIGVALUE 0U
786 | (0U)
818 | (0U)
[all …]
A Dsys_vim.h216 | (0U << 2U)\
217 | (0U << 3U)\
218 | (0U << 4U)\
220 | (0U << 6U)\
221 | (0U << 7U)\
222 | (0U << 8U)\
223 | (0U << 9U)\
245 | (0U << 31U)
248 | (0U << 1U)\
306 | (0U << 26U)\
[all …]
/bsp/rm48x50/HALCoGen/source/
A Dgio.c39 gioPORTA->DOUT = 0U /* Bit 0 */ in gioInit()
40 | (0U << 1U) /* Bit 1 */ in gioInit()
41 | (0U << 2U) /* Bit 2 */ in gioInit()
42 | (0U << 3U) /* Bit 3 */ in gioInit()
43 | (0U << 4U) /* Bit 4 */ in gioInit()
44 | (0U << 5U) /* Bit 5 */ in gioInit()
45 | (0U << 6U) /* Bit 6 */ in gioInit()
46 | (0U << 7U); /* Bit 7 */ in gioInit()
49 gioPORTA->DIR = 0U /* Bit 0 */ in gioInit()
50 | (0U << 1U) /* Bit 1 */ in gioInit()
[all …]
A Dsys_vim.c182 | (0U << 2U) in vimInit()
183 | (0U << 3U) in vimInit()
184 | (0U << 4U) in vimInit()
186 | (0U << 6U) in vimInit()
213 vimREG->REQMASKSET1 = 0U in vimInit()
246 vimREG->REQMASKSET2 = 0U in vimInit()
272 | (0U << 26U) in vimInit()
279 vimREG->REQMASKSET3 = 0U in vimInit()
305 | (0U << 26U) in vimInit()
455 for (i=0U; i<24U;i++) in vimGetConfigValue()
[all …]
/bsp/renesas/ra8d1-ek/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h171 #define BSP_TZ_CFG_LVDSAR (0U)
203 #define BSP_TZ_CFG_CGFSAR (0U)
218 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
244 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
276 #define BSP_TZ_CFG_DTC_USED (0U)
298 ((1U) << 0U) | /* SRAMSA0 */\
341 …SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x…
359 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
363 #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
367 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
[all …]
/bsp/renesas/ra8d1-vision-board/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h171 #define BSP_TZ_CFG_LVDSAR (0U)
203 #define BSP_TZ_CFG_CGFSAR (0U)
218 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
244 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
276 #define BSP_TZ_CFG_DTC_USED (0U)
298 ((1U) << 0U) | /* SRAMSA0 */\
341 …SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x…
359 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
363 #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
367 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
[all …]
/bsp/renesas/ra8m1-ek/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h170 #define BSP_TZ_CFG_LVDSAR (0U)
198 #define BSP_TZ_CFG_CGFSAR (0U)
213 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
239 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
271 #define BSP_TZ_CFG_DTC_USED (0U)
293 ((1U) << 0U) | /* SRAMSA0 */\
336 …SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x…
354 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
358 #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
362 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
[all …]
/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h82 (((1 > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
193 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
220 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
248 #define BSP_TZ_CFG_DTC_USED (0U)
308 …SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7…
326 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
330 #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
334 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
338 #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
342 #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
[all …]
/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h88 (((1 > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
196 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
223 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
251 #define BSP_TZ_CFG_DTC_USED (0U)
316 …SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7…
334 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
338 #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
342 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
350 #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
354 #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
[all …]
/bsp/renesas/ra6m4-iot/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h83 (((1 > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
193 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
220 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
248 #define BSP_TZ_CFG_DTC_USED (0U)
308 …SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7…
326 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
330 #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
334 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
338 #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
342 #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
[all …]
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/ra6e2/
A Dbsp_feature.h49 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
50 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
51 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U)
52 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U)
53 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
61 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
64 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
66 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
84 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U)
89 #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U)
[all …]
/bsp/renesas/ra4m2-eco/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h88 (((1 > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
92 (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
97 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
98 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
195 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
222 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
250 #define BSP_TZ_CFG_DTC_USED (0U)
274 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
310 …SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7…
328 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
[all …]
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/ra6m3/
A Dbsp_feature.h62 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
63 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
64 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U)
65 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U)
66 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
69 #define BSP_FEATURE_ADC_HAS_ADBUF (0U)
72 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
75 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
77 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
98 #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U)
[all …]
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/ra2l1/
A Dbsp_feature.h58 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
60 #define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U)
61 #define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0U)
65 #define BSP_FEATURE_ADC_HAS_PGA (0U)
66 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
67 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
71 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U)
72 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0U)
74 #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U)
79 #define BSP_FEATURE_ADC_HAS_ADBUF (0U)
[all …]
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/ra4m2/
A Dbsp_feature.h62 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
63 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
64 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U)
65 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U)
66 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
72 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
73 #define BSP_FEATURE_ADC_HAS_PGA (0U)
74 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
75 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
77 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
[all …]
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/
A Dbsp_feature.h62 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
63 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
64 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U)
65 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U)
66 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
72 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
73 #define BSP_FEATURE_ADC_HAS_PGA (0U)
74 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
75 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
77 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
[all …]
/bsp/renesas/ra6e2-fpb/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h77 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CEC */ | \
78 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C0 */ | \
83 (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
88 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
89 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
177 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
203 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
231 #define BSP_TZ_CFG_DTC_USED (0U)
255 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
305 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
[all …]
/bsp/renesas/ra4e2-eco/ra_cfg/fsp_cfg/bsp/
A Dbsp_mcu_family_cfg.h77 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CEC */ | \
82 (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
88 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
89 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
144 #define BSP_TZ_CFG_LVDSAR (0U)
173 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
199 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
227 #define BSP_TZ_CFG_DTC_USED (0U)
251 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
301 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
[all …]
/bsp/stm32/stm32h743-armfly-v7/board/CubeMX_Config/Inc/
A Dstm32h7xx_hal_conf.h170 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
171 #define USE_SPI_CRC 0U /*!< use CRC in SPI */
173 #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
174 #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
175 #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
176 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
177 #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
178 #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
179 #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
186 #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
[all …]
/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Inc/
A Dstm32h7xx_hal_conf.h170 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
171 #define USE_SPI_CRC 0U /*!< use CRC in SPI */
173 #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
174 #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
175 #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
176 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
177 #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
178 #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
179 #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
186 #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
[all …]
/bsp/stm32/stm32h750-artpi/board/CubeMX_Config/Core/Inc/
A Dstm32h7xx_hal_conf.h171 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
172 #define USE_SPI_CRC 0U /*!< use CRC in SPI */
174 #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
175 #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
176 #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
177 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
178 #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
179 #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
180 #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
187 #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
[all …]
/bsp/stm32/stm32h750-fk750m1-vbt6/board/CubeMX_Config/Inc/
A Dstm32h7xx_hal_conf.h171 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
172 #define USE_SPI_CRC 0U /*!< use CRC in SPI */
174 #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
175 #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
176 #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
177 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
178 #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
179 #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
180 #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
187 #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
[all …]
/bsp/stm32/stm32h723-st-nucleo/board/CubeMX_Config/Inc/
A Dstm32h7xx_hal_conf.h171 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
172 #define USE_SPI_CRC 0U /*!< use CRC in SPI */
174 #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
175 #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
176 #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
177 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
178 #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
179 #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
180 #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
187 #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
[all …]
/bsp/stm32/stm32h730-esphosted-evb/board/CubeMX_Config/Core/Inc/
A Dstm32h7xx_hal_conf.h170 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
171 #define USE_SPI_CRC 0U /*!< use CRC in SPI */
173 #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
174 #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
175 #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
176 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
177 #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
178 #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
179 #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
186 #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
[all …]
/bsp/stm32/stm32h750-weact-ministm32h7xx/board/CubeMX_Config/Inc/
A Dstm32h7xx_hal_conf.h167 #define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
168 #define USE_RTOS 0U
169 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
170 #define USE_SPI_CRC 0U /*!< use CRC in SPI */
172 #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
173 #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
174 #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
175 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
176 #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
185 #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
[all …]

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