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Searched refs:UART0_BASE (Results 1 – 25 of 107) sorted by relevance

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/bsp/loongson/ls1bdev/drivers/
A Ddrv_uart.h20 #define UART0_BASE 0xBFE40000 macro
48 #define UART0_DAT HWREG8(UART0_BASE + 0x00)
49 #define UART0_IER HWREG8(UART0_BASE + 0x01)
50 #define UART0_IIR HWREG8(UART0_BASE + 0x02)
51 #define UART0_FCR HWREG8(UART0_BASE + 0x02)
52 #define UART0_LCR HWREG8(UART0_BASE + 0x03)
53 #define UART0_MCR HWREG8(UART0_BASE + 0x04)
54 #define UART0_LSR HWREG8(UART0_BASE + 0x05)
55 #define UART0_MSR HWREG8(UART0_BASE + 0x06)
57 #define UART0_LSB HWREG8(UART0_BASE + 0x00)
[all …]
/bsp/loongson/ls1cdev/drivers/
A Ddrv_uart.h20 #define UART0_BASE 0xBFE40000 macro
48 #define UART0_DAT HWREG8(UART0_BASE + 0x00)
49 #define UART0_IER HWREG8(UART0_BASE + 0x01)
50 #define UART0_IIR HWREG8(UART0_BASE + 0x02)
51 #define UART0_FCR HWREG8(UART0_BASE + 0x02)
52 #define UART0_LCR HWREG8(UART0_BASE + 0x03)
53 #define UART0_MCR HWREG8(UART0_BASE + 0x04)
54 #define UART0_LSR HWREG8(UART0_BASE + 0x05)
55 #define UART0_MSR HWREG8(UART0_BASE + 0x06)
57 #define UART0_LSB HWREG8(UART0_BASE + 0x00)
[all …]
/bsp/lm3s8962/drivers/
A Dboard.c112 UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, in rt_hw_console_init()
121 while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); in rt_hw_console_putc()
123 while(UARTCharPutNonBlocking(UART0_BASE, c) == false); in rt_hw_console_putc()
A Dserial.c159 if (serial->hw_base == UART0_BASE) in rt_serial_open()
308 serial->hw_base = UART0_BASE; in rt_hw_serial_init()
322 UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, in rt_hw_serial_init()
/bsp/lm3s9b9x/drivers/
A Dboard.c113 UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, in rt_hw_console_init()
122 while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); in rt_hw_console_putc()
124 while(UARTCharPutNonBlocking(UART0_BASE, c) == false); in rt_hw_console_putc()
A Dserial.c159 if (serial->hw_base == UART0_BASE) in rt_serial_open()
308 serial->hw_base = UART0_BASE; in rt_hw_serial_init()
322 UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, in rt_hw_serial_init()
/bsp/lm4f232/drivers/
A Dboard.c121 UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, in rt_hw_console_init()
130 while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); in rt_hw_console_putc()
132 while(UARTCharPutNonBlocking(UART0_BASE, c) == false); in rt_hw_console_putc()
A Dserial.c159 if (serial->hw_base == UART0_BASE) in rt_serial_open()
308 serial->hw_base = UART0_BASE; in rt_hw_serial_init()
322 UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, in rt_hw_serial_init()
/bsp/bluetrum/libraries/hal_drivers/
A Ddrv_usart.c41 .instance = UART0_BASE,
183 case (rt_uint32_t)UART0_BASE: in ab32_getc()
242 if(hal_uart_getflag(UART0_BASE, UART_FLAG_RXPND)) //RX one byte finish in uart_isr()
244 uart_obj[0].rx_buf[uart_obj[0].rx_idx++ % 10] = hal_uart_read(UART0_BASE); in uart_isr()
245 hal_uart_clrflag(UART0_BASE, UART_FLAG_RXPND); in uart_isr()
/bsp/mini4020/drivers/
A Dboard.c24 #define UART0 ((struct uartport *)UART0_BASE)
153 *(RP)(UART0_BASE) = c; in rt_hw_serial_putc()
/bsp/tm4c129x/libraries/driverlib/
A Duart.c73 { UART0_BASE, INT_UART0_TM4C123 },
86 { UART0_BASE, INT_UART0_TM4C129 },
116 return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) || in _UARTBaseValid()
819 ASSERT((ui32Base == UART0_BASE) || in UARTModemControlSet()
871 ASSERT((ui32Base == UART0_BASE) || in UARTModemControlClear()
917 ASSERT((ui32Base == UART0_BASE) || in UARTModemControlGet()
957 ASSERT((ui32Base == UART0_BASE) || in UARTModemStatusGet()
/bsp/mipssim/drivers/
A Dmipssim.h9 #define UART0_BASE KSEG1ADDR(ISA_MMIO_BASE + UART0_ISA_OFF) macro
/bsp/raspberry-pi/raspi4-32/driver/
A Ddrv_uart.c71 if(uart->hw_base == UART0_BASE) in uart_configure()
226 PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE; in rt_hw_uart_isr()
262 UART0_BASE,
/bsp/raspberry-pi/raspi4-64/drivers/
A Ddrv_uart.c286 UART0_BASE,
334 uart0_addr = UART0_BASE; in rt_hw_uart_init()
336 uart0_addr = (size_t)rt_ioremap((void*)UART0_BASE, 0x1000); in rt_hw_uart_init()
/bsp/msp432e401y-LaunchPad/libraries/Drivers/config/
A Duart_config.h23 .uartbase = UART0_BASE, \
/bsp/tm4c123bsp/libraries/Drivers/config/
A Duart_config.h23 .uartbase = UART0_BASE, \
/bsp/loongson/ls2kdev/drivers/
A Dls2k1000.h12 #define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF) macro
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Include/
A Defm32g880f128.h286 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ macro
328 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
A Defm32g880f32.h286 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ macro
328 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
A Defm32g880f64.h286 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ macro
328 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
A Defm32g890f128.h286 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ macro
328 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
A Defm32g890f32.h286 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ macro
328 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
A Defm32g890f64.h286 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ macro
328 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
/bsp/cvitek/drivers/
A Ddrv_uart.h23 #define UART0_BASE 0x04140000 macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/
A Dbl602_memorymap.h51 #define UART0_BASE ((uint32_t)0x4000A000) macro

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