1 /* 2 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0. 5 * 6 * @Date: 2021-03-31 14:59:20 7 * @LastEditTime: 2021-04-02 14:14:34 8 * @Description: This files is for definition of uart register 9 * 10 * @Modify History: * * Ver Who Date Changes 11 * ----- ------ -------- -------------------------------------- 12 */ 13 14 #ifndef FT_UART_HW_H 15 #define FT_UART_HW_H 16 17 #ifdef __cplusplus 18 extern "C" 19 { 20 #endif 21 22 #include "ft_types.h" 23 #include "ft_assert.h" 24 #include "ft_io.h" 25 26 /************************** Constant Definitions *****************************/ 27 28 /** @name Register Map 29 * 30 * Register offsets for the UART. 31 * @{ 32 */ 33 34 #define UARTDR_OFFSET 0U /* 数据寄存器 */ 35 #define UARTRSR_OFFSET 4U /* 接收状态寄存器/错误清除寄存器 */ 36 #define UARTECR_OFFSET UARTRSR_OFFSET 37 #define UARTFTR_OFFSET 0x18U /* 标志寄存器 */ 38 #define UARTILPR_OFFSET 0x020U /* 低功耗计数寄存器 */ 39 #define UARTIBRD_OFFSET 0x024U /* 波特率整数值配置寄存器 */ 40 #define UARTFBRD_OFFSET 0x028U /* 波特率小数值配置寄存器 */ 41 #define UARTLCR_H_OFFSET 0x02cU /* 线控寄存器 */ 42 #define UARTCR_OFFSET 0x030U /* 控制寄存器 */ 43 #define UARTIFLS_OFFSET 0x034U /* FIFO阈值选择寄存器 */ 44 #define UARTIMSC_OFFSET 0x038U /* 中断屏蔽选择清除寄存器 */ 45 #define UARTRIS_OFFSET 0x03cU /* 中断状态寄存器 */ 46 #define UARTMIS_OFFSET 0x040U /* 中断屏蔽状态寄存器 */ 47 #define UARTICR_OFFSET 0x044U /* 中断清除寄存器 */ 48 #define UARTDMACR_OFFSET 0x048U /* DMA控制寄存器 */ 49 50 /* 数据寄存器 RW */ 51 52 #define UARTDR_OE 0x800U /* 如果接收到数据并且接收的 FIFO 已满，该位设置为 1 */ 53 #define UARTDR_BE 0x400U /* 突发错误 */ 54 #define UARTDR_PE 0x200U /* 奇偶校验错误。 */ 55 #define UARTDR_FE 0x100U /* 帧错误。 */ 56 #define UARTDR_ALLE (UARTDR_OE | UARTDR_BE | UARTDR_PE | UARTDR_FE) 57 #define UARTDR_DATA 0xffU /* R 接收数据 ，W 传输数据 */ 58 59 /* 接收状态寄存器 RW */ 60 61 #define UARTRSR_OE 0x8U /* 溢出错误。 */ 62 #define UARTRSR_BE 0x4U /* 突发错误 */ 63 #define UARTRSR_PE 0x2U /* 奇偶校验错误。 */ 64 #define UARTRSR_FE 0x1U /* 帧错误 */ 65 66 #define UARTECR_CLE 0xffU /* 清除 */ 67 68 /* 标志寄存器 RO */ 69 #define UARTFTR_RI 0x100U /* Ring indicator */ 70 #define UARTFTR_TXFE 0x80U /* Transmit FIFO empty */ 71 #define UARTFTR_RXFF 0x40U /* Receive FIFO full */ 72 #define UARTFTR_TXFF 0x20U /* Transmit FIFO full. */ 73 #define UARTFTR_RXFE 0x10U /* Receive FIFO empty */ 74 #define UARTFTR_BUSY 0x08U /* UART busy */ 75 #define UARTFTR_DCD 0x04U /* Data carrier detect. */ 76 #define UARTFTR_DSR 0x02U /* Data set ready. */ 77 #define UARTFTR_CTS 0x1U /* Clear to send */ 78 79 /* IrDA 低功耗计数寄存器 RW */ 80 #define UARTILPR_ILPDVSR 0xffU /* 8-bit low-power divisor value. These bits are cleared to 0 at reset */ 81 82 /* 波特率整数值配置寄存器 RW */ 83 #define UARTIBRD_BAUD_DIVFRAC 0xffffU /* The fractional baud rate divisor. */ 84 85 /* 波特率小数值配置寄存器 RW */ 86 #define UARTFBRD_BAUD_DIVFRAC 0x3fU /* The fractional baud rate divisor. */ 87 88 /* 线控寄存器 RW */ 89 #define UARTLCR_H_SPS 0x80U /* Stick parity select. */ 90 #define UARTLCR_H_WLEN 0x60U /* Word length. */ 91 #define UARTLCR_H_FEN 0x10U /* Enable FIFOs. */ 92 #define UARTLCR_H_STP2 0x08U /* Two stop bits select. */ 93 #define UARTLCR_H_EPS 0x04U /* Even parity select. */ 94 #define UARTLCR_H_PEN 0x02U /* Parity enable. */ 95 #define UARTLCR_H_BRK 0x01U /* send break */ 96 97 /* 控制寄存器 RW */ 98 #define UARTCR_CTSEN 0x8000U /* CTS hardware flow control enable. */ 99 #define UARTCR_RTSEN 0x4000U /* RTS hardware flow control enable. */ 100 #define UARTCR_OUT2 0x2000U /* This bit is the complement of the UART Out2 (nUARTOut2) modem status output. */ 101 #define UARTCR_Out1 0x1000U /* This bit is the complement of the UART Out1 (nUARTOut1) modem status output. */ 102 #define UARTCR_RTS 0x0800U /* Request to send. */ 103 #define UARTCR_DTR 0x0400U /* Data transmit ready */ 104 #define UARTCR_RXE 0x0200U /* Receive enable. */ 105 #define UARTCR_TXE 0x0100U /* Transmit enable. */ 106 #define UARTCR_LBE 0x0080U /* Loop back enable.*/ 107 #define UARTCR_SIRLP 0x4U /* IrDA SIR low power mode. */ 108 #define UARTCR_SIREN 0x2U /* SIR enable. */ 109 #define UARTCR_UARTEN 0x1U /* UART enable. */ 110 111 /* FIFO阈值选择寄存器 RW */ 112 #define UARTIFLS_RXIFLSEL 0x38U /* Receive interrupt FIFO level select. */ 113 #define UARTIFLS_TXIFLSEL 0x7U /* Transmit interrupt FIFO level select. */ 114 115 /* 中断屏蔽选择清除寄存器 RW */ 116 #define UARTIMSC_OEIM 0x400U /* Overrun error interrupt mask. */ 117 #define UARTIMSC_BEIM 0x200U /* Break error interrupt mask */ 118 #define UARTIMSC_PEIM 0x100U /* Parity error interrupt mask. */ 119 #define UARTIMSC_FEIM 0x80U /* Framing error interrupt mask. */ 120 #define UARTIMSC_RTIM 0x40U /* Receive timeout interrupt mask. */ 121 #define UARTIMSC_TXIM 0x20U /* Transmit interrupt mask. */ 122 #define UARTIMSC_RXIM 0x10U /* Receive interrupt mask. */ 123 #define UARTIMSC_DSRMIM 0x8U /* nUARTDSR modem interrupt mask. */ 124 #define UARTIMSC_DCDMIM 0x4U /* nUARTDCD modem interrupt mask. */ 125 #define UARTIMSC_CTSMIM 0x2U /* nUARTCTS modem interrupt mask. */ 126 #define UARTIMSC_RIMIM 0x1U /* nUARTRI modem interrupt mask. */ 127 #define UARTIMSC_ALLM 0x3ffU /* all interrupt mask */ 128 129 /* 中断状态寄存器 RO */ 130 131 #define UARTRIS_OEIS 0x400U /* Overrun error interrupt mask. */ 132 #define UARTRIS_BEIS 0x200U /* Break error interrupt mask */ 133 #define UARTRIS_PEIS 0x100U /* Parity error interrupt mask. */ 134 #define UARTRIS_FEIS 0x80U /* Framing error interrupt mask. */ 135 #define UARTRIS_RTIS 0x40U /* Receive timeout interrupt mask. */ 136 #define UARTRIS_TXIS 0x20U /* Transmit interrupt mask. */ 137 #define UARTRIS_RXIS 0x10U /* Receive interrupt mask. */ 138 #define UARTRIS_DSRMIS 0x8U /* nUARTDSR modem interrupt mask. */ 139 #define UARTRIS_DCDMIS 0x4U /* nUARTDCD modem interrupt mask. */ 140 #define UARTRIS_CTSMIS 0x2U /* nUARTCTS modem interrupt mask. */ 141 #define UARTRIS_RIMIS 0x1U /* nUARTRI modem interrupt mask. */ 142 143 /* 中断屏蔽状态寄存器 R0 */ 144 145 #define UARTMIS_OEMIS 0x400U /* Overrun error interrupt mask. */ 146 #define UARTMIS_BEMIS 0x200U /* Break error interrupt mask */ 147 #define UARTMIS_PEMIS 0x100U /* Parity error interrupt mask. */ 148 #define UARTMIS_FEMIS 0x80U /* Framing error interrupt mask. */ 149 #define UARTMIS_RTMIS 0x40U /* Receive timeout interrupt mask. */ 150 #define UARTMIS_TXMIS 0x20U /* Transmit interrupt mask. */ 151 #define UARTMIS_RXMIS 0x10U /* Receive interrupt mask. */ 152 #define UARTMIS_DSRMMIS 0x8U /* nUARTDSR modem interrupt mask. */ 153 #define UARTMIS_DCDMMIS 0x4U /* nUARTDCD modem interrupt mask. */ 154 #define UARTMIS_CTSMMIS 0x2U /* nUARTCTS modem interrupt mask. */ 155 #define UARTMIS_RIMMIS 0x1U /* nUARTRI modem interrupt mask. */ 156 157 /* 中断清除寄存器 WO */ 158 #define UARTICR_OEIC 0x400U /* Overrun error interrupt mask. */ 159 #define UARTICR_BEIC 0x200U /* Break error interrupt mask */ 160 #define UARTICR_PEIC 0x100U /* Parity error interrupt mask. */ 161 #define UARTICR_FEIC 0x80U /* Framing error interrupt mask. */ 162 #define UARTICR_RTIC 0x40U /* Receive timeout interrupt mask. */ 163 #define UARTICR_TXIC 0x20U /* Transmit interrupt mask. */ 164 #define UARTICR_RXIC 0x10U /* Receive interrupt mask. */ 165 #define UARTICR_DSRMIC 0x8U /* nUARTDSR modem interrupt mask. */ 166 #define UARTICR_DCDMIC 0x4U /* nUARTDCD modem interrupt mask. */ 167 #define UARTICR_CTSMIC 0x2U /* nUARTCTS modem interrupt mask. */ 168 #define UARTICR_RIMIC 0x1U /* nUARTRI modem interrupt mask. */ 169 170 /* DMA控制寄存器 RW */ 171 #define UARTDMACR_DMAONERR 0x4U /* DMA on error. */ 172 #define UARTDMACR_TXDMAE 0x2U /* Transmit DMA enable. */ 173 #define UARTDMACR_RXDMAE 0x1U /* Receive DMA enable. */ 174 175 /***************** Macros (Inline Functions) Definitions *********************/ 176 177 /** 178 * @name: FT_UART_ReadReg 179 * @msg: 读取串口寄存器 180 * @param {u32} BaseAddress 串口的基地址 181 * @param {u32} RegOffset 串口的寄存器的偏移 182 * @return {u32} 寄存器参数 183 */ 184 #define FT_UART_ReadReg(BaseAddress, RegOffset) Ft_in32(BaseAddress + (u32)RegOffset) 185 186 /** 187 * @name: FT_UART_WriteReg 188 * @msg: 写入串口寄存器 189 * @param {u32} BaseAddress 串口的基地址 190 * @param {u32} RegOffset 串口的寄存器的偏移 191 * @param {u32} RegisterValue 写入寄存器参数 192 * @return {void} 193 */ 194 #define FT_UART_WriteReg(BaseAddress, RegOffset, RegisterValue) Ft_out32(BaseAddress + (u32)RegOffset, (u32)RegisterValue) 195 196 /** 197 * @name: FT_UART_ISRECEIVEDATA 198 * @msg: 用于确认是否接收到数据 199 * @param {u32} BaseAddress 串口的基地址 200 * @return {bool} true 是存在数据 ， false 是不存在数据 201 * 202 */ 203 #define FT_UART_IsReceiveData(BaseAddress) (Ft_in32(BaseAddress + UARTFTR_OFFSET) & UARTFTR_RXFE) 204 205 /** 206 * @name: FT_UART_ISTRANSMITFULL 207 * @msg: 用于确认是否能够发送数据 208 * @param {u32} BaseAddress 串口的基地址 209 * @return {bool} true 是数据已满 ， false 可以发送数据 210 */ 211 #define FT_UART_IsTransmitFull(BaseAddress) ((Ft_in32(BaseAddress + UARTFTR_OFFSET) & (u32)UARTFTR_TXFF) == UARTFTR_TXFF) 212 213 void FUart_SendByte(u32 BaseAddress, u8 Byte); 214 u8 FUart_RecvByte(u32 BaseAddress); 215 u8 FUart_GetChar(u32 BaseAddress); 216 217 #ifdef __cplusplus 218 } 219 #endif 220 221 #endif 222