| /bsp/rockchip/rk3568/driver/ |
| A D | drv_uart.c | 54 #define UART_FCR 2 /* Out: FIFO Control Register */ macro
142 … dw8250_write32(addr, UART_FCR, UART_FCR_EN_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); in dw8250_write32()
168 dw8250_write32(base, UART_FCR, UART_FCR_EN_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); in dw8250_uart_configure()
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| /bsp/ultrarisc/drivers/ |
| A D | drv_uart.h | 31 #define UART_FCR 2 macro
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| A D | drv_uart.c | 61 write8_uart(uart->hw_base, UART_FCR, UART_FCR_FIFO_ENABLE | UART_FCR_FIFO_CLEAR); in _uart_configure()
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| /bsp/k230/drivers/interdrv/uart/ |
| A D | drv_uart.c | 29 #define UART_FCR (0x08) /* FIFO control register */ macro
164 write32(uart_base + UART_FCR, 0x01); in _uart_init()
172 read32(uart_base + UART_FCR); in _uart_init()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/uart/ |
| A D | hal_uart.c | 316 hal_writeb(uart_priv->fcr, uart_base + UART_FCR); in uart_set_fifo()
362 hal_writeb(UART_FCR_FIFO_EN, uart_base + UART_FCR); in uart_force_idle()
365 | UART_FCR_FIFO_EN, uart_base + UART_FCR); in uart_force_idle()
366 hal_writeb(0, uart_base + UART_FCR); in uart_force_idle()
369 hal_writeb(uart_priv->fcr, uart_base + UART_FCR); in uart_force_idle()
370 (void)hal_readb(uart_base + UART_FCR); in uart_force_idle()
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| A D | uart.h | 50 #define UART_FCR (0x08) /* FIFO control register */ macro
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| /bsp/qemu-virt64-riscv/driver/ |
| A D | drv_uart.h | 30 #define UART_FCR 2 macro
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| A D | drv_uart.c | 48 write8_uart0(UART_FCR, UART_FCR_FIFO_ENABLE | UART_FCR_FIFO_CLEAR); in uart_init()
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| /bsp/xuantie/virt64/c906/board/ |
| A D | drv_uart.h | 30 #define UART_FCR 2 macro
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| A D | drv_uart.c | 48 write8_uart0(UART_FCR, UART_FCR_FIFO_ENABLE | UART_FCR_FIFO_CLEAR); in uart_init()
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| /bsp/allwinner/libraries/drivers/ |
| A D | drv_uart.c | 230 #define UART_FCR (0x08) /* FIFO control register */ macro
543 hal_writeb(fcr, uart_base + UART_FCR); in uart_set_fifo()
822 hal_writeb(UART_FCR_FIFO_EN, uart_base + UART_FCR); in uart_irq_handler()
823 … hal_writeb(UART_FCR_TXFIFO_RST | UART_FCR_RXFIFO_RST | UART_FCR_FIFO_EN, uart_base + UART_FCR); in uart_irq_handler()
824 hal_writeb(0, uart_base + UART_FCR); in uart_irq_handler()
827 (void)hal_readb(uart_base + UART_FCR); in uart_irq_handler()
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| /bsp/cvitek/drivers/ |
| A D | drv_uart.h | 58 #define UART_FCR 2 /* Out: FIFO Control Register */ macro
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| A D | drv_uart.c | 94 dw8250_write32(addr, UART_FCR, UART_FCR_DEFVAL); in dw8250_write32()
130 dw8250_write32(base, UART_FCR, UART_FCR_DEFVAL); in dw8250_uart_configure()
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| /bsp/allwinner_tina/drivers/ |
| A D | drv_uart.h | 25 #define UART_FCR (0X08) macro
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| /bsp/beaglebone/drivers/ |
| A D | uart_reg.h | 19 #define UART_FCR(base) (base + 0x8) macro
67 #define UART_FCR_REG(base) REG16(UART_FCR(base))
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| /bsp/loongson/ls2kdev/drivers/ |
| A D | drv_uart.h | 21 #define UART_FCR(base) HWREG8(base + 0x02) macro
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| A D | drv_uart.c | 61 UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */ in ls2k_uart_configure()
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| /bsp/mipssim/drivers/ |
| A D | drv_uart.h | 21 #define UART_FCR(base) HWREG8(base + 0x02) macro
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| A D | drv_uart.c | 41 UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */ in mipssim_uart_configure()
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| /bsp/loongson/ls1bdev/drivers/ |
| A D | drv_uart.h | 38 #define UART_FCR(base) HWREG8(base + 0x02) macro
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| /bsp/loongson/ls1cdev/drivers/ |
| A D | drv_uart.h | 38 #define UART_FCR(base) HWREG8(base + 0x02) macro
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| /bsp/rockchip/rk3500/driver/uart8250/ |
| A D | regs.h | 40 #define UART_FCR 2 /* Out: FIFO Control Register */ macro
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| A D | early.c | 52 serial8250_early_out(serial, UART_FCR, 0); /* no fifo */ in init_serial()
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| A D | 8250-dw.c | 81 …serial->serial_out(serial, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_X… in dw8250_check_lcr()
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| A D | core.c | 220 …serial->serial_out(serial, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_X… in serial8250_uart_configure()
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