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Searched refs:UART_LCR (Results 1 – 25 of 30) sorted by relevance

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/bsp/rockchip/rk3568/driver/
A Ddrv_uart.c35 #define UART_LCR 3 /* Out: Line Control Register */ macro
128 if (offset == UART_LCR) in dw8250_write32()
135 unsigned int lcr = dw8250_read32(addr, UART_LCR); in dw8250_write32()
178 dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) | UART_LCR_DLAB); in dw8250_uart_configure()
182 dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) & (~UART_LCR_DLAB)); in dw8250_uart_configure()
184 …dw8250_write32(base, UART_LCR, (dw8250_read32(base, UART_LCR) & (~UART_LCR_WLEN8)) | UART_LCR_WLEN… in dw8250_uart_configure()
185 dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) & (~UART_LCR_STOP)); in dw8250_uart_configure()
186 dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) & (~UART_LCR_PARITY)); in dw8250_uart_configure()
/bsp/rockchip/rk3500/driver/uart8250/
A Dcore.c231 serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) | UART_LCR_DLAB); in serial8250_uart_configure()
235 … serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) & (~UART_LCR_DLAB)); in serial8250_uart_configure()
237 … serial->serial_out(serial, UART_LCR, (serial->serial_in(serial, UART_LCR) & (~wlen)) | wlen); in serial8250_uart_configure()
238 … serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) & (~UART_LCR_STOP)); in serial8250_uart_configure()
239 … serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) & (~UART_LCR_PARITY)); in serial8250_uart_configure()
A Dearly.c49 serial8250_early_out(serial, UART_LCR, 0x3); /* 8n1 */ in init_serial()
58 c = serial8250_early_in(serial, UART_LCR); in init_serial()
59 serial8250_early_out(serial, UART_LCR, c | UART_LCR_DLAB); in init_serial()
62 serial8250_early_out(serial, UART_LCR, c & ~UART_LCR_DLAB); in init_serial()
A D8250-dw.c68 void *offset = (void *)(serial->base + (UART_LCR << serial->regshift)); in dw8250_check_lcr()
74 rt_uint32_t lcr = serial->serial_in(serial, UART_LCR); in dw8250_check_lcr()
105 if (offset == UART_LCR && !dw8250->uart_16550_compatible) in dw8250_serial_out32()
A Dfiq-debugger.c118 rockchip_fiq_write(t, 0x83, UART_LCR); in fiq_debugger_uart_configure()
122 rockchip_fiq_write(t, 0x03, UART_LCR); in fiq_debugger_uart_configure()
/bsp/allwinner_tina/drivers/
A Ddrv_uart.c199 val = readl(addr + UART_LCR); in uart_configure()
201 writel(val, addr + UART_LCR); in uart_configure()
205 val = readl(addr + UART_LCR); in uart_configure()
207 writel(val, addr + UART_LCR); in uart_configure()
209 val = readl(addr + UART_LCR); in uart_configure()
212 writel(val, addr + UART_LCR); in uart_configure()
A Ddrv_uart.h26 #define UART_LCR (0X0C) macro
/bsp/cvitek/drivers/
A Ddrv_uart.c80 if (offset == UART_LCR) in dw8250_write32()
87 unsigned int lcr = dw8250_read32(addr, UART_LCR); in dw8250_write32()
105 int lcr_val = dw8250_read32(addr, UART_LCR) & ~UART_LCR_BKSE; in dw8250_uart_setbrg()
107 dw8250_write32(addr, UART_LCR, UART_LCR_BKSE | lcr_val); in dw8250_uart_setbrg()
111 dw8250_write32(addr, UART_LCR, lcr_val); in dw8250_uart_setbrg()
133 dw8250_write32(base, UART_LCR, UART_LCR_8N1); in dw8250_uart_configure()
A Ddrv_uart.h63 #define UART_LCR 3 /* Out: Line Control Register */ macro
/bsp/nxp/lpc/lpc2148/drivers/
A Dserial.c26 #define UART_LCR(base) REG8(base + 0x0C) macro
328 UART_LCR(lpc_serial->hw_base) = 0x83; in rt_hw_serial_init()
335 UART_LCR(lpc_serial->hw_base) = 0x03; in rt_hw_serial_init()
366 UART_LCR(lpc_serial->hw_base) = 0x83; in rt_hw_serial_init()
373 UART_LCR(lpc_serial->hw_base) = 0x03; in rt_hw_serial_init()
/bsp/nxp/lpc/lpc2478/drivers/
A Dserial.c26 #define UART_LCR(base) REG8(base + 0x0C) macro
301 UART_LCR(lpc_serial->hw_base) = 0x83; in rt_hw_serial_init()
308 UART_LCR(lpc_serial->hw_base) = 0x03; in rt_hw_serial_init()
339 UART_LCR(lpc_serial->hw_base) = 0x83; in rt_hw_serial_init()
346 UART_LCR(lpc_serial->hw_base) = 0x03; in rt_hw_serial_init()
/bsp/loongson/ls2kdev/drivers/
A Ddrv_uart.c44 UART_LCR(uart_dev->base) = 0x80; // Activate buadcfg in ls2k_uart_set_buad()
48 UART_LCR(uart_dev->base) = CFCR_8BITS; // Back to normal in ls2k_uart_set_buad()
63 UART_LCR(uart_dev->base) = 0x3; in ls2k_uart_configure()
A Ddrv_uart.h22 #define UART_LCR(base) HWREG8(base + 0x03) macro
/bsp/k230/drivers/interdrv/uart/
A Ddrv_uart.c30 #define UART_LCR (0x0c) /* line control register */ macro
148 write32(uart_base + UART_LCR, 0x00); in _uart_init()
152 write32(uart_base + UART_LCR, 0x80); in _uart_init()
162 write32(uart_base + UART_LCR, 0x03); in _uart_init()
/bsp/qemu-virt64-riscv/driver/
A Ddrv_uart.c38 write8_uart0(UART_LCR, UART_LCR_BAUD_LATCH); in uart_init()
46 write8_uart0(UART_LCR, UART_LCR_EIGHT_BITS); in uart_init()
A Ddrv_uart.h38 #define UART_LCR 3 macro
/bsp/xuantie/virt64/c906/board/
A Ddrv_uart.c38 write8_uart0(UART_LCR, UART_LCR_BAUD_LATCH); in uart_init()
46 write8_uart0(UART_LCR, UART_LCR_EIGHT_BITS); in uart_init()
A Ddrv_uart.h38 #define UART_LCR 3 macro
/bsp/ultrarisc/drivers/
A Ddrv_uart.h39 #define UART_LCR 3 macro
A Ddrv_uart.c51 write8_uart(uart->hw_base, UART_LCR, UART_LCR_BAUD_LATCH); in _uart_configure()
59 write8_uart(uart->hw_base, UART_LCR, UART_LCR_EIGHT_BITS); in _uart_configure()
/bsp/allwinner/libraries/drivers/
A Ddrv_uart.c231 #define UART_LCR (0x0c) /* line control register */ macro
455 lcr = hal_readb(uart_base + UART_LCR); in uart_set_baudrate()
459 hal_writeb(lcr | UART_LCR_DLAB, uart_base + UART_LCR); in uart_set_baudrate()
471 hal_writeb(lcr, uart_base + UART_LCR); in uart_set_baudrate()
482 lcr = hal_readb(uart_base + UART_LCR); in uart_set_format()
531 hal_writeb(lcr, uart_base + UART_LCR); in uart_set_format()
/bsp/allwinner/libraries/sunxi-hal/hal/source/uart/
A Dhal_uart.c193 value = hal_readb(uart_base + UART_LCR); in uart_set_format()
243 hal_writeb(uart_priv->lcr, uart_base + UART_LCR); in uart_set_format()
294 hal_writeb(uart_priv->lcr | UART_LCR_DLAB, uart_base + UART_LCR); in uart_set_baudrate()
306 hal_writeb(uart_priv->lcr, uart_base + UART_LCR); in uart_set_baudrate()
389 hal_writeb(uart_priv->lcr, uart_base + UART_LCR); in uart_handle_busy()
/bsp/beaglebone/drivers/
A Duart_reg.h21 #define UART_LCR(base) (base + 0xC) macro
69 #define UART_LCR_REG(base) REG16(UART_LCR(base))
/bsp/mipssim/drivers/
A Ddrv_uart.h22 #define UART_LCR(base) HWREG8(base + 0x03) macro
/bsp/loongson/ls1bdev/drivers/
A Ddrv_uart.h39 #define UART_LCR(base) HWREG8(base + 0x03) macro

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