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Searched refs:USART_CTL1_CPL (Results 1 – 2 of 2) sorted by relevance

/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/
A Dgd32vf103_usart.c432 ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); in usart_synchronous_clock_config()
434 ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); in usart_synchronous_clock_config()
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/
A Dgd32vf103_usart.h100 #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ macro

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