| /bsp/m16c62p/drivers/ |
| A D | vectors_iar.asm | 30 DC32 os_context_switch ; Vector 0: BRK 31 DC32 0 ; Vector 1: Reserved 32 DC32 0 ; Vector 2: Reserved 33 DC32 0 ; Vector 3: Reserved 34 DC32 0 ; Vector 4: INT3 41 DC32 0 ; Vector 11: DMA0 42 DC32 0 ; Vector 12: DMA1 44 DC32 0 ; Vector 14: A/D 59 DC32 0 ; Vector 29: 60 DC32 0 ; Vector 30: [all …]
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| A D | vectors_gcc.S | 10 ; Fixed Vector Table 28 ; Variable Vector Table 38 .long _os_context_switch ; Vector 0: BRK 39 .long 0 ; Vector 1: Reserved 42 .long 0 ; Vector 4: INT3 49 .long 0 ; Vector 11: DMA0 50 .long 0 ; Vector 12: DMA1 52 .long 0 ; Vector 14: A/D 67 .long 0 ; Vector 29: 68 .long 0 ; Vector 30: [all …]
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| /bsp/qemu-virt64-riscv/ |
| A D | Kconfig | 30 bool "Using RISC-V Vector Extension" 36 prompt "Vector Registers Length in Bits"
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| /bsp/m16c62p/ |
| A D | m16c62p.ld | 13 /* Variable Vector Section */ 161 /* Fixed Vector Section */
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| /bsp/qemu-virt64-riscv/applications/test/test_vector/ |
| A D | SConscript | 7 group = DefineGroup('Vector', src, depend = [''], CPPPATH = CPPPATH)
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ |
| A D | ht32f5xxxx_aes.c | 376 void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector) in AES_SetVectorTable() argument 384 HT_AESn->IVR[i] = __REV(*&Vector[i]); in AES_SetVectorTable() 386 HT_AESn->IVR[i] = *&Vector[i]; in AES_SetVectorTable()
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ |
| A D | ht32f1xxxx_aes.c | 374 void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector) in AES_SetVectorTable() argument 382 HT_AESn->IVR[i] = __REV(*&Vector[i]); in AES_SetVectorTable() 384 HT_AESn->IVR[i] = *&Vector[i]; in AES_SetVectorTable()
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| /bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/ |
| A D | flashdebug.ini | 4 _WDWORD(0xE000ED08, 0); // Setup Vector Table Offset Register
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| /bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/ |
| A D | flashdebug.ini | 4 _WDWORD(0xE000ED08, 0); // Setup Vector Table Offset Register
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| /bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/ |
| A D | flashdebug.ini | 4 _WDWORD(0xE000ED08, 0); // Setup Vector Table Offset Register
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| /bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/ |
| A D | flashdebug.ini | 4 _WDWORD(0xE000ED08, 0); // Setup Vector Table Offset Register
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| /bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/ |
| A D | flashdebug.ini | 4 _WDWORD(0xE000ED08, 0); // Setup Vector Table Offset Register
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| /bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/ |
| A D | flashdebug.ini | 4 _WDWORD(0xE000ED08, 0); // Setup Vector Table Offset Register
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| /bsp/k230/ |
| A D | Kconfig | 51 bool "Double-precision floating-point with Vector"
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| /bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/ |
| A D | startup_hc32l136.s | 76 ; Vector Table Mapped to Address 0 at Reset 158 ; reset Vector table address.
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| /bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/ARM/ |
| A D | startup_hc32l19x.s | 76 ; Vector Table Mapped to Address 0 at Reset 161 ; reset Vector table address.
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| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_02_cm0plus.s | 29 ; Vector Table Mapped to Address 0 at Reset 123 ; Update Vector Table Offset Register. */
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| /bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_02_cm0plus.s | 29 ; Vector Table Mapped to Address 0 at Reset 123 ; Update Vector Table Offset Register. */
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| /bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_04_cm0plus.s | 29 ; Vector Table Mapped to Address 0 at Reset 123 ; Update Vector Table Offset Register. */
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| /bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_03_cm0plus.s | 29 ; Vector Table Mapped to Address 0 at Reset 123 ; Update Vector Table Offset Register. */
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| /bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_02_cm0plus.s | 29 ; Vector Table Mapped to Address 0 at Reset 123 ; Update Vector Table Offset Register. */
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| /bsp/xuantie/xiaohui/c910/ |
| A D | README.md | 15 • RISC-V 64GC[V] 指令架构;(C910 不支持 Vector)
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| /bsp/xuantie/xiaohui/c907/ |
| A D | README.md | 16 • 可选配矢量指令扩展,支持 Vector Extention 1.0 版本,支持 INT8/INT16/INT32/INT64 以及
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| /bsp/xuantie/xiaohui/c908/ |
| A D | README.md | 16 • 可选配矢量指令扩展,支持 Vector Extention 1.0 版本,支持 INT8/INT16/INT32/INT64 以及
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| /bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/TOOLCHAIN_IAR/ |
| A D | startup_cm0plus.s | 91 ;* Vector Table and RAM Vector Table 162 ; Update Vector Table Offset Register with address of user ROM table
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