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Searched refs:WRITE_REG (Results 1 – 25 of 221) sorted by relevance

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/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_dma.c261 WRITE_REG(DMAx->CFG, 0x0); in ald_dma_reset()
262 WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); in ald_dma_reset()
263 WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); in ald_dma_reset()
264 WRITE_REG(DMAx->CHENCLR, 0xFFF); in ald_dma_reset()
265 WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); in ald_dma_reset()
266 WRITE_REG(DMAx->CHPRCLR, 0xFFF); in ald_dma_reset()
267 WRITE_REG(DMAx->ERRCLR, 0x1); in ald_dma_reset()
268 WRITE_REG(DMAx->IER, 0x0); in ald_dma_reset()
269 WRITE_REG(DMAx->ICFR, 0x80000FFF); in ald_dma_reset()
272 WRITE_REG(DMAx->CH_SELCON[i], 0x0); in ald_dma_reset()
[all …]
A Dald_gpio.c209 WRITE_REG(GPIOx->MODE, tmp); in ald_gpio_init()
215 WRITE_REG(GPIOx->ODOS, tmp); in ald_gpio_init()
221 WRITE_REG(GPIOx->PUPD, tmp); in ald_gpio_init()
227 WRITE_REG(GPIOx->ODRV, tmp); in ald_gpio_init()
237 WRITE_REG(GPIOx->FLT, tmp); in ald_gpio_init()
243 WRITE_REG(GPIOx->TYPE, tmp); in ald_gpio_init()
251 i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); in ald_gpio_init()
427 WRITE_REG(GPIOx->BIR, pin); in ald_gpio_toggle_pin()
468 WRITE_REG(GPIOx->MODE, tmp); in ald_gpio_toggle_dir()
488 WRITE_REG(GPIOx->LOCK, pin); in ald_gpio_lock_pin()
[all …]
A Dald_wdt.c67 WRITE_REG(WWDT->LOAD, load); in ald_wwdt_init()
117 WRITE_REG(WWDT->INTCLR, 1); in ald_wwdt_clear_flag_status()
128 WRITE_REG(WWDT->INTCLR, 0x1); in ald_wwdt_feed_dog()
152 WRITE_REG(IWDT->LOAD, load); in ald_iwdt_init()
201 WRITE_REG(IWDT->INTCLR, 1); in ald_iwdt_clear_flag_status()
212 WRITE_REG(IWDT->INTCLR, 1); in ald_iwdt_feed_dog()
A Dald_calc.c67 WRITE_REG(CALC->RDCND, data); in ald_calc_sqrt()
84 WRITE_REG(CALC->DIVDR, dividend); in ald_calc_div()
85 WRITE_REG(CALC->DIVSR, divisor); in ald_calc_div()
104 WRITE_REG(CALC->DIVDR, dividend); in ald_calc_div_sign()
105 WRITE_REG(CALC->DIVSR, divisor); in ald_calc_div_sign()
A Dald_rmu.c105 WRITE_REG(RMU->CRSTSR, state); in ald_rmu_clear_reset_status()
127 WRITE_REG(RMU->AHB1RSTR, pos); in ald_rmu_reset_periperal()
131 WRITE_REG(RMU->AHB2RSTR, pos); in ald_rmu_reset_periperal()
135 WRITE_REG(RMU->APB1RSTR, pos); in ald_rmu_reset_periperal()
139 WRITE_REG(RMU->APB2RSTR, pos); in ald_rmu_reset_periperal()
A Dald_flash.c96 WRITE_REG(MSC->FLASHCR, 0x0); in flash_lock()
128 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); in flash_page_erase()
181 WRITE_REG(MSC->FLASHFIFO, p_data[0]); in flash_word_program()
182 WRITE_REG(MSC->FLASHFIFO, p_data[1]); in flash_word_program()
185 WRITE_REG(MSC->FLASHDL, p_data[0]); in flash_word_program()
186 WRITE_REG(MSC->FLASHDH, p_data[1]); in flash_word_program()
187 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); in flash_word_program()
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_dma.c275 WRITE_REG(DMAx->CFG, 0x0); in ald_dma_reset()
276 WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); in ald_dma_reset()
277 WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); in ald_dma_reset()
278 WRITE_REG(DMAx->CHENCLR, 0xFFF); in ald_dma_reset()
279 WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); in ald_dma_reset()
280 WRITE_REG(DMAx->CHPRCLR, 0xFFF); in ald_dma_reset()
281 WRITE_REG(DMAx->ERRCLR, 0x1); in ald_dma_reset()
282 WRITE_REG(DMAx->IER, 0x0); in ald_dma_reset()
283 WRITE_REG(DMAx->ICFR, 0x80000FFF); in ald_dma_reset()
286 WRITE_REG(DMAx->CH_SELCON[i], 0x0); in ald_dma_reset()
[all …]
A Dald_gpio.c211 WRITE_REG(GPIOx->MODE, tmp); in ald_gpio_init()
217 WRITE_REG(GPIOx->ODOS, tmp); in ald_gpio_init()
223 WRITE_REG(GPIOx->PUPD, tmp); in ald_gpio_init()
229 WRITE_REG(GPIOx->PODRV, tmp); in ald_gpio_init()
245 WRITE_REG(GPIOx->FLT, tmp); in ald_gpio_init()
251 WRITE_REG(GPIOx->TYPE, tmp); in ald_gpio_init()
259 i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); in ald_gpio_init()
436 WRITE_REG(GPIOx->BIR, pin); in ald_gpio_toggle_pin()
477 WRITE_REG(GPIOx->MODE, tmp); in ald_gpio_toggle_dir()
497 WRITE_REG(GPIOx->LOCK, pin); in ald_gpio_lock_pin()
[all …]
A Dald_wdt.c67 WRITE_REG(WWDT->LOAD, load); in ald_wwdt_init()
117 WRITE_REG(WWDT->INTCLR, 1); in ald_wwdt_clear_flag_status()
130 WRITE_REG(WWDT->INTCLR, 0x1); in ald_wwdt_feed_dog()
156 WRITE_REG(IWDT->LOAD, load); in ald_iwdt_init()
206 WRITE_REG(IWDT->INTCLR, 1); in ald_iwdt_clear_flag_status()
220 WRITE_REG(IWDT->INTCLR, 1); in ald_iwdt_feed_dog()
A Dald_rmu.c106 WRITE_REG(RMU->CRSTSR, state); in ald_rmu_clear_reset_status()
128 WRITE_REG(RMU->AHB1RSTR, pos); in ald_rmu_reset_periperal()
132 WRITE_REG(RMU->AHB2RSTR, pos); in ald_rmu_reset_periperal()
136 WRITE_REG(RMU->APB1RSTR, pos); in ald_rmu_reset_periperal()
140 WRITE_REG(RMU->APB2RSTR, pos); in ald_rmu_reset_periperal()
A Dald_flash.c117 WRITE_REG(MSC->FLASHCR, 0x0); in flash_lock()
149 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); in flash_page_erase()
202 WRITE_REG(MSC->FLASHFIFO, p_data[0]); in flash_word_program()
203 WRITE_REG(MSC->FLASHFIFO, p_data[1]); in flash_word_program()
206 WRITE_REG(MSC->FLASHDL, p_data[0]); in flash_word_program()
207 WRITE_REG(MSC->FLASHDH, p_data[1]); in flash_word_program()
208 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); in flash_word_program()
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_pwm.c112 WRITE_REG(pPWM->pReg->INTSTS, status & 0xf); in HAL_PWM_IRQHandler()
157 WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); in HAL_PWM_SetConfig()
159 WRITE_REG(PWM_PERIOD_REG(pPWM, channel), period); in HAL_PWM_SetConfig()
160 WRITE_REG(PWM_DUTY_REG(pPWM, channel), duty); in HAL_PWM_SetConfig()
170 WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); in HAL_PWM_SetConfig()
196 WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); in HAL_PWM_SetOneshot()
222 WRITE_REG(PWM_CTRL_REG(pPWM, channel), ctrl); in HAL_PWM_SetCapturedFreq()
308 WRITE_REG(pPWM->pReg->INT_EN, intEnable); in HAL_PWM_Enable()
315 WRITE_REG(PWM_CTRL_REG(pPWM, channel), enableConf); in HAL_PWM_Enable()
339 WRITE_REG(pPWM->pReg->INT_EN, intEnable); in HAL_PWM_Disable()
[all …]
A Dhal_dwdma.c41 WRITE_REG(reg, ((mask) << 8) | (mask))
43 WRITE_REG(reg, ((mask) << 8) | 0)
168 WRITE_REG(reg->DMACFGREG, 0); in DWDMA_off()
185 WRITE_REG(reg->DMACFGREG, DW_CFG_DMA_EN); in DWDMA_on()
207 WRITE_REG(dwc->creg->CFG_LO, cfglo); in DWC_initialize()
208 WRITE_REG(dwc->creg->CFG_HI, cfghi); in DWC_initialize()
228 WRITE_REG(dw->pReg->CLEAR.TFR, dwc->mask); in DWC_deinitialize()
231 WRITE_REG(dw->pReg->CLEAR.ERR, dwc->mask); in DWC_deinitialize()
258 WRITE_REG(dw->pReg->CLEAR.ERR, dwc->mask); in DWC_HandleError()
488 WRITE_REG(dwc->creg->CTL_LO, ctllo); in HAL_DWDMA_Start()
[all …]
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_dma.h773 #define __LL_DMA_RegTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->TIMR, val)
812 #define __LL_DMA_RegBTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->BTIMR, val)
851 #define __LL_DMA_RegSTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->STIMR, val)
890 #define __LL_DMA_RegDTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->DTIMR, val)
952 #define __LL_DMA_RegTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->TCR, val)
975 #define __LL_DMA_RegBTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->BTCR, val)
998 #define __LL_DMA_RegSTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->STCR, val)
1021 #define __LL_DMA_RegDTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->DTCR, val)
1044 #define __LL_DMA_RegTECR_Write(__DMA__, val) WRITE_REG((__DMA__)->TECR, val)
1067 #define __LL_DMA_RegCR0_Write(__DMA__, val) WRITE_REG((__DMA__)->CR0, val)
[all …]
A Dtae32f53xx_ll_iwdg.h140 #define __LL_IWDG_ENABLE_WRITE_ACCESS(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWD…
147 #define __LL_IWDG_DISABLE_WRITE_ACCESS(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWD…
155 #define __LL_IWDG_START(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWD…
162 #define __LL_IWDG_STOP(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWD…
207 #define __LL_IWDG_CLEAR_FLAG(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->SR, (__FL…
227 #define __LL_IWDG_RELOAD_COUNTER(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWD…
A Dtae32f53xx_ll_flash.h202 #define __LL_FLASH_STANDBY_ENABLE() do{ WRITE_REG(FLASH->LPR, FLASH_PWR_KEY); \
212 #define __LL_FLASH_WAKEUP_ENABLE() do{ WRITE_REG(FLASH->LPR, FLASH_PWR_KEY); \
249 #define __LL_FLASH_CLEAR_PENDING_FLAG(__FLAG__) WRITE_REG(FLASH->ISR, (__FLAG__))
294 WRITE_REG(FLASH->KEYR, FLASH_KEY1); in LL_FLASH_Unlock()
295 WRITE_REG(FLASH->KEYR, FLASH_KEY2); in LL_FLASH_Unlock()
329 WRITE_REG(FLASH->KEYR, FLASH_OP_KEY); in LL_FLASH_PF_Unlock()
343 WRITE_REG(FLASH->KEYR, 0x00000000UL); in LL_FLASH_PF_Lock()
/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/
A Dald_gpio.c207 WRITE_REG(GPIOx->MODE, tmp); in ald_gpio_init()
213 WRITE_REG(GPIOx->OD, tmp); in ald_gpio_init()
219 WRITE_REG(GPIOx->PUPD, tmp); in ald_gpio_init()
235 WRITE_REG(GPIOx->FLT, tmp); in ald_gpio_init()
249 i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); in ald_gpio_init()
286 WRITE_REG(GPIOx->FUNC0, 0x00); in ald_gpio_func_default()
287 WRITE_REG(GPIOx->FUNC1, 0x00); in ald_gpio_func_default()
416 WRITE_REG(GPIOx->BIR, pin); in ald_gpio_toggle_pin()
477 WRITE_REG(GPIOx->LOCK, pin); in ald_gpio_lock_pin()
504 WRITE_REG(GPIOx->DOUT, val); in ald_gpio_write_port()
[all …]
A Dald_dma.c221 WRITE_REG(DMA->IDR, 0x3FFF); in ald_dma_reset()
222 WRITE_REG(DMA->ICR, 0x3FFF); in ald_dma_reset()
227 WRITE_REG(DMA->CHANNEL[i].CON, 0x0); in ald_dma_reset()
228 WRITE_REG(DMA->CHANNEL[i].SAR, 0x0); in ald_dma_reset()
229 WRITE_REG(DMA->CHANNEL[i].DAR, 0x0); in ald_dma_reset()
230 WRITE_REG(DMA->CHANNEL[i].NDT, 0x0); in ald_dma_reset()
231 WRITE_REG(DMA_MUX->CH_SELCON[i], 0x0); in ald_dma_reset()
332 WRITE_REG(DMA->CHANNEL[channel].CON, 0x0); in ald_dma_channel_config()
333 WRITE_REG(DMA->CHANNEL[channel].SAR, 0x0); in ald_dma_channel_config()
334 WRITE_REG(DMA->CHANNEL[channel].DAR, 0x0); in ald_dma_channel_config()
[all …]
A Dald_wdt.c64 WRITE_REG(WWDT->LOAD, load); in ald_wwdt_init()
115 WRITE_REG(WWDT->INTCLR, 0x55AA); in ald_wwdt_clear_flag_status()
128 WRITE_REG(WWDT->INTCLR, 0xFFFFFFFF); in ald_wwdt_feed_dog()
152 WRITE_REG(IWDT->LOAD, load); in ald_iwdt_init()
202 WRITE_REG(IWDT->INTCLR, 0x55AA); in ald_iwdt_clear_flag_status()
214 WRITE_REG(IWDT->INTCLR, 0xFFFFFFFF); in ald_iwdt_feed_dog()
A Dald_adc.c131 WRITE_REG(hperh->perh->CCR, 0x0); in ald_adc_init()
158 WRITE_REG(hperh->perh->CLR, 0x30F); in ald_adc_reset()
159 WRITE_REG(hperh->perh->CON0, 0x0); in ald_adc_reset()
160 WRITE_REG(hperh->perh->CON1, 0x0); in ald_adc_reset()
161 WRITE_REG(hperh->perh->CCR, 0x0); in ald_adc_reset()
163 WRITE_REG(hperh->perh->WDTL, 0x0); in ald_adc_reset()
169 WRITE_REG(hperh->perh->ICHS, 0x0); in ald_adc_reset()
170 WRITE_REG(hperh->perh->NCHS1, 0x0); in ald_adc_reset()
171 WRITE_REG(hperh->perh->NCHS2, 0x0); in ald_adc_reset()
172 WRITE_REG(hperh->perh->NCHS3, 0x0); in ald_adc_reset()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_iwdg.h108 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
143 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
154 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
165 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
176 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
195 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); in LL_IWDG_SetPrescaler()
225 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); in LL_IWDG_SetReloadCounter()
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/
A Dtae32f53xx_ll_iir.c89 WRITE_REG(Instance->CR0, (Init->Order | Init->BufferReset)); in LL_IIR_Init()
181 WRITE_REG(Instance->SCALR, (((uint32_t)(Config->InDataScale << IIR_SCALR_DISCAL_Pos)) | in LL_IIR_FilterConfig()
186 WRITE_REG(Instance->DIAR, Config->InDataAddress); in LL_IIR_FilterConfig()
190 … WRITE_REG(Instance->AxCOEFR[idx], ((uint32_t)(Config->AxCOEF[idx]) & IIR_AxCOEFR_AxCOEF_Msk)); in LL_IIR_FilterConfig()
194 … WRITE_REG(Instance->BxCOEFR[idx], ((uint32_t)(Config->BxCOEF[idx]) & IIR_BxCOEFR_BxCOEF_Msk)); in LL_IIR_FilterConfig()
220 WRITE_REG(Instance->SCALSR, (((uint32_t)(Config->InDataScale << IIR_SCALSR_DISCALS_Pos)) | in LL_IIR_FilterConfig_Preload()
225 WRITE_REG(Instance->DIASR, Config->InDataAddress); in LL_IIR_FilterConfig_Preload()
229 … WRITE_REG(Instance->AxCOEFSR[idx], ((uint32_t)(Config->AxCOEF[idx]) & IIR_AxCOEFSR_AxCOEFS_Msk)); in LL_IIR_FilterConfig_Preload()
233 … WRITE_REG(Instance->BxCOEFSR[idx], ((uint32_t)(Config->BxCOEF[idx]) & IIR_BxCOEFSR_BxCOEFS_Msk)); in LL_IIR_FilterConfig_Preload()
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/
A Dald_tsense.h52 #define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
53 #define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
99 WRITE_REG(TSENSE->LTGR, (data)); \
105 WRITE_REG(TSENSE->HTGR, (data)); \
111 WRITE_REG(TSENSE->TBDR, (data)); \
117 WRITE_REG(TSENSE->TCALBDR, (data)); \
A Dald_wdt.h70 #define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
71 #define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
72 #define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
73 #define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/
A Dald_tsense.h54 #define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
55 #define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
101 WRITE_REG(TSENSE->LTGR, (data)); \
107 WRITE_REG(TSENSE->HTGR, (data)); \
113 WRITE_REG(TSENSE->TBDR, (data)); \
119 WRITE_REG(TSENSE->TCALBDR, (data)); \

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