Searched refs:WRITE_REG_MASK_WE (Results 1 – 4 of 4) sorted by relevance
| /bsp/rockchip/rk2108/board/common/ |
| A D | iomux_base.c | 47 WRITE_REG_MASK_WE(GRF->SOC_CON5, in uart1_m0_iomux_config()
59 WRITE_REG_MASK_WE(GRF->SOC_CON5, in uart1_m1_iomux_config()
71 WRITE_REG_MASK_WE(GRF->SOC_CON5, in uart1_m2_iomux_config()
86 WRITE_REG_MASK_WE(GRF->SOC_CON5, in uart1_m3_iomux_config()
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| /bsp/rockchip/common/rk_hal/lib/hal/src/cru/ |
| A D | hal_cru.c | 377 WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); in HAL_CRU_SetPllFreq()
383 WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); in HAL_CRU_SetPllFreq()
384 WRITE_REG_MASK_WE(*(pSetup->conOffset3), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); in HAL_CRU_SetPllFreq()
390 WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); in HAL_CRU_SetPllFreq()
420 WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); in HAL_CRU_SetPllPowerUp()
445 WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); in HAL_CRU_SetPllPowerDown()
539 WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); in HAL_CRU_SetPllFreq()
545 WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); in HAL_CRU_SetPllFreq()
553 WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); in HAL_CRU_SetPllFreq()
589 WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); in HAL_CRU_SetPllPowerUp()
[all …]
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| /bsp/rockchip/common/rk_hal/lib/hal/inc/ |
| A D | hal_def.h | 49 #define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val))) macro
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| /bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/ |
| A D | hal_pinctrl.c | 207 WRITE_REG_MASK_WE(GRF->SOC_CON15, in PINCTRL_ExtraSet()
211 WRITE_REG_MASK_WE(GRF->SOC_CON15, in PINCTRL_ExtraSet()
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