Searched refs:WoReg (Results 1 – 25 of 129) sorted by relevance
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55 #define REG_ICM_CTRL (*(WoReg *)0x42002C04UL) /**< \brief (ICM) Control */57 #define REG_ICM_IER (*(WoReg *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */58 #define REG_ICM_IDR (*(WoReg *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */64 #define REG_ICM_UIHVAL0 (*(WoReg *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Va…65 #define REG_ICM_UIHVAL1 (*(WoReg *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Va…66 #define REG_ICM_UIHVAL2 (*(WoReg *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Va…67 #define REG_ICM_UIHVAL3 (*(WoReg *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Va…68 #define REG_ICM_UIHVAL4 (*(WoReg *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Va…69 #define REG_ICM_UIHVAL5 (*(WoReg *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Va…70 #define REG_ICM_UIHVAL6 (*(WoReg *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Va…[all …]
73 #define REG_AES_KEYWORD0 (*(WoReg *)0x4200240CUL) /**< \brief (AES) Keyword 0 */74 #define REG_AES_KEYWORD1 (*(WoReg *)0x42002410UL) /**< \brief (AES) Keyword 1 */75 #define REG_AES_KEYWORD2 (*(WoReg *)0x42002414UL) /**< \brief (AES) Keyword 2 */76 #define REG_AES_KEYWORD3 (*(WoReg *)0x42002418UL) /**< \brief (AES) Keyword 3 */77 #define REG_AES_KEYWORD4 (*(WoReg *)0x4200241CUL) /**< \brief (AES) Keyword 4 */78 #define REG_AES_KEYWORD5 (*(WoReg *)0x42002420UL) /**< \brief (AES) Keyword 5 */79 #define REG_AES_KEYWORD6 (*(WoReg *)0x42002424UL) /**< \brief (AES) Keyword 6 */80 #define REG_AES_KEYWORD7 (*(WoReg *)0x42002428UL) /**< \brief (AES) Keyword 7 */82 #define REG_AES_INTVECTV0 (*(WoReg *)0x4200243CUL) /**< \brief (AES) Initialisation Vecto…83 #define REG_AES_INTVECTV1 (*(WoReg *)0x42002440UL) /**< \brief (AES) Initialisation Vecto…[all …]
49 #define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Regis…52 #define REG_CMCC_MAINT0 (*(WoReg *)0x41006020UL) /**< \brief (CMCC) Cache Maintenance R…53 #define REG_CMCC_MAINT1 (*(WoReg *)0x41006024UL) /**< \brief (CMCC) Cache Maintenance R…56 #define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Contr…
102 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41008028UL) /**< \brief (PORT) Write Configuration…116 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410080A8UL) /**< \brief (PORT) Write Configuration…130 #define REG_PORT_WRCONFIG2 (*(WoReg *)0x41008128UL) /**< \brief (PORT) Write Configuration…144 #define REG_PORT_WRCONFIG3 (*(WoReg *)0x410081A8UL) /**< \brief (PORT) Write Configuration…
45 #define REG_PCC_IER (*(WoReg *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Reg…46 #define REG_PCC_IDR (*(WoReg *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Re…
54 #define REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) /**< \brief (QSPI) Transmit Data */63 #define REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */
157 #define REG_GMAC_IER (*(WoReg *)0x42000828UL) /**< \brief (GMAC) Interrupt Enable Re…158 #define REG_GMAC_IDR (*(WoReg *)0x4200082CUL) /**< \brief (GMAC) Interrupt Disable R…244 #define REG_GMAC_TA (*(WoReg *)0x420009D8UL) /**< \brief (GMAC) 1588 Timer Adjust R…
56 #define REG_I2S_TXDATA (*(WoReg *)0x43002830UL) /**< \brief (I2S) Tx Data */
74 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41000028UL) /**< \brief (PORT) Write Configuration…88 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410000A8UL) /**< \brief (PORT) Write Configuration…
86 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration …99 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration …
89 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration …102 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration …
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