1 /***************************************************************************** 2 * Copyright (c) 2019, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32g45x_xfmc.h 30 * @author Nations 31 * @version v1.0.1 32 * 33 * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32G45X_XFMC_H__ 36 #define __N32G45X_XFMC_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32g45x.h" 43 44 /** @addtogroup N32G45X_StdPeriph_Driver 45 * @{ 46 */ 47 48 /** @addtogroup XFMC 49 * @{ 50 */ 51 52 /** @addtogroup XFMC_Exported_Types 53 * @{ 54 */ 55 56 /** 57 * @brief Timing parameters For NOR/SRAM Banks 58 */ 59 typedef struct 60 { 61 uint32_t AddrSetTime; /*!< Defines the number of HCLK cycles to configure 62 the duration of the address setup time. 63 This parameter can be a value between 0 and 0xF. 64 @note: It is not used with synchronous NOR Flash memories. */ 65 66 uint32_t AddrHoldTime; /*!< Defines the number of HCLK cycles to configure 67 the duration of the address hold time. 68 This parameter can be a value between 0 and 0xF. 69 @note: It is not used with synchronous NOR Flash memories.*/ 70 71 uint32_t DataSetTime; /*!< Defines the number of HCLK cycles to configure 72 the duration of the data setup time. 73 This parameter can be a value between 1 and 0xFF. 74 @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ 75 76 uint32_t BusRecoveryCycle; /*!< Defines the number of HCLK cycles to configure 77 the duration of the bus turnaround. 78 This parameter can be a value between 0 and 0xF. 79 @note: It is only used for multiplexed NOR Flash memories. */ 80 81 uint32_t ClkDiv; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. 82 This parameter can be a value between 1 and 0xF. 83 @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ 84 85 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 86 to the memory before getting the first data. 87 The value of this parameter depends on the memory type as shown below: 88 - It must be set to 0 in case of a CRAM 89 - It is don't care in asynchronous NOR, SRAM or ROM accesses 90 - It may assume a value between 0 and 0xF in NOR Flash memories 91 with synchronous burst mode enable */ 92 93 uint32_t AccMode; /*!< Specifies the asynchronous access mode. 94 This parameter can be a value of @ref XFMC_Access_Mode */ 95 } XFMC_NorSramTimingInitType; 96 97 /** 98 * @brief XFMC NOR/SRAM Init structure definition 99 */ 100 101 typedef struct 102 { 103 XFMC_Bank1_Block *Block; /*!< Specifies the NOR/SRAM memory bank block that will be used. 104 This parameter can be a XFMC_BANK1_BLOCK1 or XFMC_BANK1_BLOCK2 */ 105 106 uint32_t DataAddrMux; /*!< Specifies whether the address and data values are 107 multiplexed on the databus or not. 108 This parameter can be a value of @ref XFMC_Data_Address_Bus_Multiplexing */ 109 110 uint32_t MemType; /*!< Specifies the type of external memory attached to 111 the corresponding memory bank. 112 This parameter can be a value of @ref XFMC_Memory_Type */ 113 114 uint32_t MemDataWidth; /*!< Specifies the external memory device width. 115 This parameter can be a value of @ref XFMC_Data_Width */ 116 117 uint32_t BurstAccMode; /*!< Enables or disables the burst access mode for Flash memory, 118 valid only with synchronous burst Flash memories. 119 This parameter can be a value of @ref XFMC_Burst_Access_Mode */ 120 121 uint32_t AsynchroWait; /*!< Enables or disables wait signal during asynchronous transfers, 122 valid only with asynchronous Flash memories. 123 This parameter can be a value of @ref AsynchroWait */ 124 125 uint32_t WaitSigPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 126 the Flash memory in burst mode. 127 This parameter can be a value of @ref XFMC_Wait_Signal_Polarity */ 128 129 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 130 memory, valid only when accessing Flash memories in burst mode. 131 This parameter can be a value of @ref XFMC_Wrap_Mode */ 132 133 uint32_t WaitSigConfig; /*!< Specifies if the wait signal is asserted by the memory one 134 clock cycle before the wait state or during the wait state, 135 valid only when accessing memories in burst mode. 136 This parameter can be a value of @ref XFMC_Wait_Timing */ 137 138 uint32_t WriteEnable; /*!< Enables or disables the write operation in the selected bank by the XFMC. 139 This parameter can be a value of @ref XFMC_Write_Operation */ 140 141 uint32_t WaitSigEnable; /*!< Enables or disables the wait-state insertion via wait 142 signal, valid for Flash memory access in burst mode. 143 This parameter can be a value of @ref XFMC_Wait_Signal */ 144 145 uint32_t ExtModeEnable; /*!< Enables or disables the extended mode. 146 This parameter can be a value of @ref XFMC_Extended_Mode */ 147 148 uint32_t WriteBurstEnable; /*!< Enables or disables the write burst operation. 149 This parameter can be a value of @ref XFMC_Write_Burst */ 150 151 XFMC_NorSramTimingInitType* RWTimingStruct; /*!< Timing Parameters for write and read access 152 if the ExtendedMode is not used*/ 153 154 XFMC_NorSramTimingInitType* WTimingStruct; /*!< Timing Parameters for write access if the 155 ExtendedMode is used*/ 156 } XFMC_NorSramInitTpye; 157 158 /** 159 * @brief Timing parameters For XFMC NAND and PCCARD Banks 160 */ 161 162 typedef struct 163 { 164 uint32_t SetTime; /*!< Defines the number of HCLK cycles to setup address before 165 the command assertion for NAND-Flash read or write access 166 to common/Attribute or I/O memory space (depending on 167 the memory space timing to be configured). 168 This parameter can be a value between 0 and 0xFF.*/ 169 170 uint32_t WaitSetTime; /*!< Defines the minimum number of HCLK cycles to assert the 171 command for NAND-Flash read or write access to 172 common/Attribute or I/O memory space (depending on the 173 memory space timing to be configured). 174 This parameter can be a number between 0x00 and 0xFF */ 175 176 uint32_t HoldSetTime; /*!< Defines the number of HCLK clock cycles to hold address 177 (and data for write access) after the command deassertion 178 for NAND-Flash read or write access to common/Attribute 179 or I/O memory space (depending on the memory space timing 180 to be configured). 181 This parameter can be a number between 0x00 and 0xFF */ 182 183 uint32_t HiZSetTime; /*!< Defines the number of HCLK clock cycles during which the 184 databus is kept in HiZ after the start of a NAND-Flash 185 write access to common/Attribute or I/O memory space (depending 186 on the memory space timing to be configured). 187 This parameter can be a number between 0x00 and 0xFF */ 188 } XFMC_NandTimingInitType; 189 190 /** 191 * @brief XFMC NAND Init structure definition 192 */ 193 194 typedef struct 195 { 196 XFMC_Bank23_Module *Bank; /*!< Specifies the NAND memory bank that will be used. 197 This parameter can be XFMC_BANK2 or XFMC_BANK3 */ 198 199 uint32_t WaitFeatureEnable; /*!< Enables or disables the Wait feature for the NAND Memory Bank. 200 This parameter can be any value of @ref XFMC_Wait_feature */ 201 202 uint32_t MemDataWidth; /*!< Specifies the external memory device width. 203 This parameter can be any value of @ref XFMC_Data_Width */ 204 205 uint32_t EccEnable; /*!< Enables or disables the ECC computation. 206 This parameter can be any value of @ref XFMC_Ecc */ 207 208 uint32_t EccPageSize; /*!< Defines the page size for the extended ECC. 209 This parameter can be any value of @ref XFMC_ECC_Page_Size */ 210 211 uint32_t TCLRSetTime; /*!< Defines the number of HCLK cycles to configure the 212 delay between CLE low and RE low. 213 This parameter can be a value between 0 and 0xFF. */ 214 215 uint32_t TARSetTime; /*!< Defines the number of HCLK cycles to configure the 216 delay between ALE low and RE low. 217 This parameter can be a number between 0x0 and 0xFF */ 218 219 XFMC_NandTimingInitType* CommSpaceTimingStruct; /*!< XFMC Common Space Timing */ 220 221 XFMC_NandTimingInitType* AttrSpaceTimingStruct; /*!< XFMC Attribute Space Timing */ 222 } XFMC_NandInitType; 223 224 /** 225 * @brief XFMC PCCARD Init structure definition 226 */ 227 228 typedef struct 229 { 230 uint32_t WaitFeatureEnable; /*!< Enables or disables the Wait feature for the Memory Bank. 231 This parameter can be any value of @ref XFMC_Wait_feature */ 232 233 uint32_t TCLRSetTime; /*!< Defines the number of HCLK cycles to configure the 234 delay between CLE low and RE low. 235 This parameter can be a value between 0 and 0xFF. */ 236 237 uint32_t TARSetTime; /*!< Defines the number of HCLK cycles to configure the 238 delay between ALE low and RE low. 239 This parameter can be a number between 0x0 and 0xFF */ 240 241 XFMC_NandTimingInitType* CommSpaceTimingStruct; /*!< XFMC Common Space Timing */ 242 243 XFMC_NandTimingInitType* AttrSpaceTimingStruct; /*!< XFMC Attribute Space Timing */ 244 245 XFMC_NandTimingInitType* XFMC_IOSpaceTimingStruct; /*!< XFMC IO Space Timing */ 246 } XFMC_PCCARDInitType; 247 248 /** 249 * @} 250 */ 251 252 /** @addtogroup XFMC_Exported_Constants 253 * @{ 254 */ 255 256 /** @addtogroup XFMC_NORSRAM_Bank1_Reg_ResetValue 257 * @{ 258 */ 259 #define XFMC_NOR_SRAM_CR1_RESET ((uint32_t)0x000030DB) 260 #define XFMC_NOR_SRAM_CR2_RESET ((uint32_t)0x000030D2) 261 #define XFMC_NOR_SRAM_TR_RESET ((uint32_t)0x0FFFFFFF) 262 #define XFMC_NOR_SRAM_WTR_RESET ((uint32_t)0x0FFFFFFF) 263 264 /** 265 * @} 266 */ 267 268 /** @addtogroup XFMC_NAND_Bank23_Reg_ResetValue 269 * @{ 270 */ 271 #define XFMC_NAND_CTRL_RESET ((uint32_t)0x00000018) 272 #define XFMC_NAND_STS_RESET ((uint32_t)0x00000040) 273 #define XFMC_NAND_CMEMTM_RESET ((uint32_t)0xFCFCFCFC) 274 #define XFMC_NAND_ATTMEMTM_RESET ((uint32_t)0xFCFCFCFC) 275 276 /** 277 * @} 278 */ 279 280 #define IS_XFMC_NOR_SRAM_BLOCK(BLOCK) (((BLOCK) == XFMC_BANK1_BLOCK1) || ((BLOCK) == XFMC_BANK1_BLOCK2)) 281 #define IS_XFMC_NAND_BANK(BANK) (((BANK) == XFMC_BANK2) || ((BANK) == XFMC_BANK3)) 282 283 284 /** @addtogroup NOR_SRAM_Controller 285 * @{ 286 */ 287 288 /** @addtogroup XFMC_Data_Address_Bus_Multiplexing 289 * @{ 290 */ 291 #define XFMC_NOR_SRAM_DISABLE ((uint32_t)0x00000000) 292 #define XFMC_NOR_SRAM_ENABLE (XFMC_BANK1_CR_MBEN) 293 /** 294 * @} 295 */ 296 297 /** @addtogroup XFMC_Data_Address_Bus_Multiplexing 298 * @{ 299 */ 300 #define XFMC_NOR_SRAM_MUX_DISABLE ((uint32_t)0x00000000) 301 #define XFMC_NOR_SRAM_MUX_ENABLE (XFMC_BANK1_CR_MUXEN) 302 #define IS_XFMC_NOR_SRAM_MUX(MUX) (((MUX) == XFMC_NOR_SRAM_MUX_DISABLE) || ((MUX) == XFMC_NOR_SRAM_MUX_ENABLE)) 303 /** 304 * @} 305 */ 306 307 /** @addtogroup XFMC_Memory_Type 308 * @{ 309 */ 310 #define XFMC_MEM_TYPE_SRAM ((uint32_t)0x00000000) 311 #define XFMC_MEM_TYPE_PSRAM (XFMC_BANK1_CR_MTYPE_0) 312 #define XFMC_MEM_TYPE_NOR (XFMC_BANK1_CR_MTYPE_1) 313 #define IS_XFMC_NOR_SRAM_MEMORY(MEMORY) \ 314 (((MEMORY) == XFMC_MEM_TYPE_SRAM) || ((MEMORY) == XFMC_MEM_TYPE_PSRAM) || ((MEMORY) == XFMC_MEM_TYPE_NOR)) 315 /** 316 * @} 317 */ 318 319 /** @addtogroup XFMC_Data_Width 320 * @{ 321 */ 322 #define XFMC_NOR_SRAM_DATA_WIDTH_8B ((uint32_t)0x00000000) 323 #define XFMC_NOR_SRAM_DATA_WIDTH_16B (XFMC_BANK1_CR_MDBW_0) 324 #define IS_XFMC_NOR_SRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == XFMC_NOR_SRAM_DATA_WIDTH_8B) || ((WIDTH) == XFMC_NOR_SRAM_DATA_WIDTH_16B)) 325 /** 326 * @} 327 */ 328 329 /** @addtogroup XFMC_Flash_Access_Enable 330 * @{ 331 */ 332 #define XFMC_NOR_SRAM_ACC_DISABLE ((uint32_t)0x00000000) 333 #define XFMC_NOR_SRAM_ACC_ENABLE (XFMC_BANK1_CR_ACCEN) 334 /** 335 * @} 336 */ 337 338 /** @addtogroup XFMC_Burst_Access_Mode 339 * @{ 340 */ 341 #define XFMC_NOR_SRAM_BURST_MODE_DISABLE ((uint32_t)0x00000000) 342 #define XFMC_NOR_SRAM_BURST_MODE_ENABLE (XFMC_BANK1_CR_BURSTEN) 343 #define IS_XFMC_NOR_SRAM_BURSTMODE(STATE) (((STATE) == XFMC_NOR_SRAM_BURST_MODE_DISABLE) || ((STATE) == XFMC_NOR_SRAM_BURST_MODE_ENABLE)) 344 /** 345 * @} 346 */ 347 348 /** @addtogroup XFMC_Wait_Signal_Polarity 349 * @{ 350 */ 351 #define XFMC_NOR_SRAM_WAIT_SIGNAL_LOW ((uint32_t)0x00000000) 352 #define XFMC_NOR_SRAM_WAIT_SIGNAL_HIGH (XFMC_BANK1_CR_WAITDIR) 353 #define IS_XFMC_NOR_SRAM_WAIT_POLARITY(POLARITY) \ 354 (((POLARITY) == XFMC_NOR_SRAM_WAIT_SIGNAL_LOW) || ((POLARITY) == XFMC_NOR_SRAM_WAIT_SIGNAL_HIGH)) 355 /** 356 * @} 357 */ 358 359 /** @addtogroup XFMC_Wrap_Mode 360 * @{ 361 */ 362 #define XFMC_NOR_SRAM_WRAP_DISABLE ((uint32_t)0x00000000) 363 #define XFMC_NOR_SRAM_WRAP_ENABLE (XFMC_BANK1_CR_WRAPEN) 364 #define IS_XFMC_NOR_SRAM_WRAP_MODE(MODE) (((MODE) == XFMC_NOR_SRAM_WRAP_DISABLE) || ((MODE) == XFMC_NOR_SRAM_WRAP_ENABLE)) 365 /** 366 * @} 367 */ 368 369 /** @addtogroup XFMC_Wait_Timing 370 * @{ 371 */ 372 #define XFMC_NOR_SRAM_NWAIT_BEFORE_STATE ((uint32_t)0x00000000) 373 #define XFMC_NOR_SRAM_NWAIT_DURING_STATE (XFMC_BANK1_CR_WCFG) 374 #define IS_XFMC_NOR_SRAM_WAIT_SIGNAL_ACTIVE(ACTIVE) \ 375 (((ACTIVE) == XFMC_NOR_SRAM_NWAIT_BEFORE_STATE) || ((ACTIVE) == XFMC_NOR_SRAM_NWAIT_DURING_STATE)) 376 /** 377 * @} 378 */ 379 380 /** @addtogroup XFMC_Write_Operation 381 * @{ 382 */ 383 #define XFMC_NOR_SRAM_WRITE_DISABLE ((uint32_t)0x00000000) 384 #define XFMC_NOR_SRAM_WRITE_ENABLE (XFMC_BANK1_CR_WREN) 385 #define IS_XFMC_NOR_SRAM_WRITE_OPERATION(OPERATION) (((OPERATION) == XFMC_NOR_SRAM_WRITE_DISABLE) || ((OPERATION) == XFMC_NOR_SRAM_WRITE_ENABLE)) 386 /** 387 * @} 388 */ 389 390 /** @addtogroup XFMC_Wait_Signal 391 * @{ 392 */ 393 #define XFMC_NOR_SRAM_NWAIT_DISABLE ((uint32_t)0x00000000) 394 #define XFMC_NOR_SRAM_NWAIT_ENABLE (XFMC_BANK1_CR_WAITEN) 395 #define IS_XFMC_NOR_SRAM_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == XFMC_NOR_SRAM_NWAIT_DISABLE) || ((SIGNAL) == XFMC_NOR_SRAM_NWAIT_ENABLE)) 396 /** 397 * @} 398 */ 399 400 /** @addtogroup XFMC_Extended_Mode 401 * @{ 402 */ 403 #define XFMC_NOR_SRAM_EXTENDED_DISABLE ((uint32_t)0x00000000) 404 #define XFMC_NOR_SRAM_EXTENDED_ENABLE (XFMC_BANK1_CR_EXTEN) 405 #define IS_XFMC_NOR_SRAM_EXTENDED_MODE(MODE) (((MODE) == XFMC_NOR_SRAM_EXTENDED_DISABLE) || ((MODE) == XFMC_NOR_SRAM_EXTENDED_ENABLE)) 406 /** 407 * @} 408 */ 409 410 /** @addtogroup AsynchroWait 411 * @{ 412 */ 413 #define XFMC_NOR_SRAM_ASYNC_NWAIT_DISABLE ((uint32_t)0x00000000) 414 #define XFMC_NOR_SRAM_ASYNC_NWAIT_ENABLE (XFMC_BANK1_CR_WAITASYNC) 415 #define IS_XFMC_NOR_SRAM_ASYNWAIT(STATE) (((STATE) == XFMC_NOR_SRAM_ASYNC_NWAIT_DISABLE) || ((STATE) == XFMC_NOR_SRAM_ASYNC_NWAIT_ENABLE)) 416 /** 417 * @} 418 */ 419 420 421 /** @addtogroup XFMC_Write_Burst 422 * @{ 423 */ 424 #define XFMC_NOR_SRAM_BURST_WRITE_DISABLE ((uint32_t)0x00000000) 425 #define XFMC_NOR_SRAM_BURST_WRITE_ENABLE (XFMC_BANK1_CR_BURSTWREN) 426 #define IS_XFMC_NOR_SRAM_WRITE_BURST(BURST) (((BURST) == XFMC_NOR_SRAM_BURST_WRITE_DISABLE) || ((BURST) == XFMC_NOR_SRAM_BURST_WRITE_ENABLE)) 427 /** 428 * @} 429 */ 430 431 /** 432 * @} End of NOR_SRAM_Controller 433 */ 434 435 436 /** @addtogroup NOR_SRAM_Time_Control 437 * @{ 438 */ 439 440 /** @addtogroup XFMC_Address_Setup_Time 441 * @{ 442 */ 443 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_1HCLK (0x0UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 444 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_2HCLK (0x1UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 445 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_3HCLK (0x2UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 446 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_4HCLK (0x3UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 447 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_5HCLK (0x4UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 448 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_6HCLK (0x5UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 449 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_7HCLK (0x6UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 450 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_8HCLK (0x7UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 451 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_9HCLK (0x8UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 452 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_10HCLK (0x9UL << XFMC_BANK1_TR_ADDBLD_SHIFT) 453 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_11HCLK (0xAUL << XFMC_BANK1_TR_ADDBLD_SHIFT) 454 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_12HCLK (0xBUL << XFMC_BANK1_TR_ADDBLD_SHIFT) 455 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_13HCLK (0xCUL << XFMC_BANK1_TR_ADDBLD_SHIFT) 456 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_14HCLK (0xDUL << XFMC_BANK1_TR_ADDBLD_SHIFT) 457 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_15HCLK (0xEUL << XFMC_BANK1_TR_ADDBLD_SHIFT) 458 #define XFMC_NOR_SRAM_ADDR_SETUP_TIME_16HCLK (0xFUL << XFMC_BANK1_TR_ADDBLD_SHIFT) 459 #define IS_XFMC_NOR_SRAM_ADDR_SETUP_TIME(TIME) (0==((TIME) & (~XFMC_BANK1_TR_ADDBLD_MASK))) 460 /** 461 * @} 462 */ 463 464 /** @addtogroup XFMC_Address_Hold_Time 465 * @{ 466 */ 467 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_1HCLK (0x0UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 468 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_2HCLK (0x1UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 469 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_3HCLK (0x2UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 470 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_4HCLK (0x3UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 471 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_5HCLK (0x4UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 472 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_6HCLK (0x5UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 473 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_7HCLK (0x6UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 474 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_8HCLK (0x7UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 475 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_9HCLK (0x8UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 476 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_10HCLK (0x9UL << XFMC_BANK1_TR_ADDHLD_SHIFT) 477 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_11HCLK (0xAUL << XFMC_BANK1_TR_ADDHLD_SHIFT) 478 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_12HCLK (0xBUL << XFMC_BANK1_TR_ADDHLD_SHIFT) 479 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_13HCLK (0xCUL << XFMC_BANK1_TR_ADDHLD_SHIFT) 480 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_14HCLK (0xDUL << XFMC_BANK1_TR_ADDHLD_SHIFT) 481 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_15HCLK (0xEUL << XFMC_BANK1_TR_ADDHLD_SHIFT) 482 #define XFMC_NOR_SRAM_ADDR_HOLD_TIME_16HCLK (0xFUL << XFMC_BANK1_TR_ADDHLD_SHIFT) 483 #define IS_XFMC_NOR_SRAM_ADDR_HOLD_TIME(TIME) (0==((TIME) & (~XFMC_BANK1_TR_ADDHLD_MASK))) 484 /** 485 * @} 486 */ 487 488 /** @addtogroup XFMC_Data_Setup_Time 489 * @{ 490 */ 491 #define XFMC_NOR_SRAM_DATA_SETUP_TIME_MIN (0x01UL << XFMC_BANK1_TR_DATABLD_SHIFT) 492 #define XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX (0xFFUL << XFMC_BANK1_TR_DATABLD_SHIFT) 493 #define XFMC_NOR_SRAM_DATA_SETUP_TIME(x) ((x) << XFMC_BANK1_TR_DATABLD_SHIFT) 494 #define IS_XFMC_NOR_SRAM_DATASETUP_TIME(TIME) ( ((TIME) >= XFMC_NOR_SRAM_DATA_SETUP_TIME_MIN) \ 495 && ((TIME) <= XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX) ) 496 /** 497 * @} 498 */ 499 500 /** @addtogroup XFMC_Bus_Recovery_Time 501 * @{ 502 */ 503 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_1HCLK (0x0UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 504 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_2HCLK (0x1UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 505 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_3HCLK (0x2UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 506 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_4HCLK (0x3UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 507 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_5HCLK (0x4UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 508 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_6HCLK (0x5UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 509 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_7HCLK (0x6UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 510 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_8HCLK (0x7UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 511 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_9HCLK (0x8UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 512 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_10HCLK (0x9UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 513 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_11HCLK (0xAUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 514 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_12HCLK (0xBUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 515 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_13HCLK (0xCUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 516 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_14HCLK (0xDUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 517 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_15HCLK (0xEUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 518 #define XFMC_NOR_SRAM_BUSRECOVERY_TIME_16HCLK (0xFUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) 519 #define IS_XFMC_NOR_SRAM_BUSRECOVERY_TIME(TIME) (0==((TIME) & (~XFMC_BANK1_TR_BUSRECOVERY_MASK))) 520 /** 521 * @} 522 */ 523 524 /** @addtogroup XFMC_CLK_Division 525 * @{ 526 */ 527 #define XFMC_NOR_SRAM_CLK_DIV_2 (0x1UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 528 #define XFMC_NOR_SRAM_CLK_DIV_3 (0x2UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 529 #define XFMC_NOR_SRAM_CLK_DIV_4 (0x3UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 530 #define XFMC_NOR_SRAM_CLK_DIV_5 (0x4UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 531 #define XFMC_NOR_SRAM_CLK_DIV_6 (0x5UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 532 #define XFMC_NOR_SRAM_CLK_DIV_7 (0x6UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 533 #define XFMC_NOR_SRAM_CLK_DIV_8 (0x7UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 534 #define XFMC_NOR_SRAM_CLK_DIV_9 (0x8UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 535 #define XFMC_NOR_SRAM_CLK_DIV_10 (0x9UL << XFMC_BANK1_TR_CLKDIV_SHIFT) 536 #define XFMC_NOR_SRAM_CLK_DIV_11 (0xAUL << XFMC_BANK1_TR_CLKDIV_SHIFT) 537 #define XFMC_NOR_SRAM_CLK_DIV_12 (0xBUL << XFMC_BANK1_TR_CLKDIV_SHIFT) 538 #define XFMC_NOR_SRAM_CLK_DIV_13 (0xCUL << XFMC_BANK1_TR_CLKDIV_SHIFT) 539 #define XFMC_NOR_SRAM_CLK_DIV_14 (0xDUL << XFMC_BANK1_TR_CLKDIV_SHIFT) 540 #define XFMC_NOR_SRAM_CLK_DIV_15 (0xEUL << XFMC_BANK1_TR_CLKDIV_SHIFT) 541 #define XFMC_NOR_SRAM_CLK_DIV_16 (0xFUL << XFMC_BANK1_TR_CLKDIV_SHIFT) 542 #define IS_XFMC_NOR_SRAM_CLK_DIV(DIV) ( ((DIV) >= XFMC_NOR_SRAM_CLK_DIV_2) \ 543 && ((DIV) <= XFMC_NOR_SRAM_CLK_DIV_16) ) 544 /** 545 * @} 546 */ 547 548 /** @addtogroup XFMC_Data_Latency 549 * @{ 550 */ 551 #define XFMC_NOR_SRAM_DATA_LATENCY_2CLK (0x0UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 552 #define XFMC_NOR_SRAM_DATA_LATENCY_3CLK (0x1UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 553 #define XFMC_NOR_SRAM_DATA_LATENCY_4CLK (0x2UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 554 #define XFMC_NOR_SRAM_DATA_LATENCY_5CLK (0x3UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 555 #define XFMC_NOR_SRAM_DATA_LATENCY_6CLK (0x4UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 556 #define XFMC_NOR_SRAM_DATA_LATENCY_7CLK (0x5UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 557 #define XFMC_NOR_SRAM_DATA_LATENCY_8CLK (0x6UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 558 #define XFMC_NOR_SRAM_DATA_LATENCY_9CLK (0x7UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 559 #define XFMC_NOR_SRAM_DATA_LATENCY_10CLK (0x8UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 560 #define XFMC_NOR_SRAM_DATA_LATENCY_11CLK (0x9UL << XFMC_BANK1_TR_DATAHLD_SHIFT) 561 #define XFMC_NOR_SRAM_DATA_LATENCY_12CLK (0xAUL << XFMC_BANK1_TR_DATAHLD_SHIFT) 562 #define XFMC_NOR_SRAM_DATA_LATENCY_13CLK (0xBUL << XFMC_BANK1_TR_DATAHLD_SHIFT) 563 #define XFMC_NOR_SRAM_DATA_LATENCY_14CLK (0xCUL << XFMC_BANK1_TR_DATAHLD_SHIFT) 564 #define XFMC_NOR_SRAM_DATA_LATENCY_15CLK (0xDUL << XFMC_BANK1_TR_DATAHLD_SHIFT) 565 #define XFMC_NOR_SRAM_DATA_LATENCY_16CLK (0xEUL << XFMC_BANK1_TR_DATAHLD_SHIFT) 566 #define XFMC_NOR_SRAM_DATA_LATENCY_17CLK (0xFUL << XFMC_BANK1_TR_DATAHLD_SHIFT) 567 #define IS_XFMC_NOR_SRAM_DATA_LATENCY(TIME) (0==((TIME) & (~XFMC_BANK1_TR_DATAHLD_MASK))) 568 /** 569 * @} 570 */ 571 572 /** @addtogroup XFMC_Access_Mode 573 * @{ 574 */ 575 #define XFMC_NOR_SRAM_ACC_MODE_A ((uint32_t)0x00000000) 576 #define XFMC_NOR_SRAM_ACC_MODE_B (0x1UL << XFMC_BANK1_TR_ACCMODE_SHIFT) 577 #define XFMC_NOR_SRAM_ACC_MODE_C (0x2UL << XFMC_BANK1_TR_ACCMODE_SHIFT) 578 #define XFMC_NOR_SRAM_ACC_MODE_D (0x3UL << XFMC_BANK1_TR_ACCMODE_SHIFT) 579 #define IS_XFMC_NOR_SRAM_ACCESS_MODE(MODE) ( ((MODE) == XFMC_NOR_SRAM_ACC_MODE_A) || ((MODE) == XFMC_NOR_SRAM_ACC_MODE_B) \ 580 || ((MODE) == XFMC_NOR_SRAM_ACC_MODE_C) || ((MODE) == XFMC_NOR_SRAM_ACC_MODE_D) ) 581 /** 582 * @} End of NOR_SRAM_Time_Control 583 */ 584 585 /** 586 * @} 587 */ 588 589 /** @addtogroup NAND_Controller 590 * @{ 591 */ 592 593 /** @addtogroup XFMC_Wait_feature 594 * @{ 595 */ 596 #define XFMC_NAND_NWAIT_DISABLE ((uint32_t)0x00000000) 597 #define XFMC_NAND_NWAIT_ENABLE (XFMC_CTRL_WAITEN) 598 #define IS_XFMC_NAND_WAIT_FEATURE(FEATURE) \ 599 (((FEATURE) == XFMC_NAND_NWAIT_DISABLE) || ((FEATURE) == XFMC_NAND_NWAIT_ENABLE)) 600 /** 601 * @} 602 */ 603 604 /** @addtogroup XFMC_Nand_Enable 605 * @{ 606 */ 607 #define XFMC_NAND_BANK_DISABLE ((uint32_t)0x00000000) 608 #define XFMC_NAND_BANK_ENABLE (XFMC_CTRL_BANKEN) 609 /** 610 * @} 611 */ 612 613 /** @addtogroup XFMC_Bank23_Memory_Type 614 * @{ 615 */ 616 #define XFMC_BANK23_MEM_TYPE_NAND (XFMC_CTRL_MEMTYPE) 617 #define IS_XFMC_BANK23_MEM_TYPE(TYPE) ((TYPE) == XFMC_BANK23_MEM_TYPE_NAND) 618 /** 619 * @} 620 */ 621 622 /** @addtogroup XFMC_Wait_feature 623 * @{ 624 */ 625 #define XFMC_NAND_BUS_WIDTH_8B ((uint32_t)0x00000000) 626 #define XFMC_NAND_BUS_WIDTH_16B (XFMC_CTRL_BUSWID_0) 627 #define IS_XFMC_NAND_BUS_WIDTH(WIDTH) (((WIDTH) == XFMC_NAND_BUS_WIDTH_8B)||((WIDTH) == XFMC_NAND_BUS_WIDTH_16B)) 628 /** 629 * @} 630 */ 631 632 /** @addtogroup XFMC_Ecc 633 * @{ 634 */ 635 #define XFMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) 636 #define XFMC_NAND_ECC_ENABLE (XFMC_CTRL_ECCEN) 637 #define IS_XFMC_ECC_STATE(STATE) (((STATE) == XFMC_NAND_ECC_DISABLE) || ((STATE) == XFMC_NAND_ECC_ENABLE)) 638 /** 639 * @} 640 */ 641 642 /** @addtogroup XFMC_CLE_RE_Delay 643 * @{ 644 */ 645 #define XFMC_NAND_CLE_DELAY_1HCLK (0x0UL << XFMC_CTRL_CRDLY_SHIFT) 646 #define XFMC_NAND_CLE_DELAY_2HCLK (0x1UL << XFMC_CTRL_CRDLY_SHIFT) 647 #define XFMC_NAND_CLE_DELAY_3HCLK (0x2UL << XFMC_CTRL_CRDLY_SHIFT) 648 #define XFMC_NAND_CLE_DELAY_4HCLK (0x3UL << XFMC_CTRL_CRDLY_SHIFT) 649 #define XFMC_NAND_CLE_DELAY_5HCLK (0x4UL << XFMC_CTRL_CRDLY_SHIFT) 650 #define XFMC_NAND_CLE_DELAY_6HCLK (0x5UL << XFMC_CTRL_CRDLY_SHIFT) 651 #define XFMC_NAND_CLE_DELAY_7HCLK (0x6UL << XFMC_CTRL_CRDLY_SHIFT) 652 #define XFMC_NAND_CLE_DELAY_8HCLK (0x7UL << XFMC_CTRL_CRDLY_SHIFT) 653 #define XFMC_NAND_CLE_DELAY_9HCLK (0x8UL << XFMC_CTRL_CRDLY_SHIFT) 654 #define XFMC_NAND_CLE_DELAY_10HCLK (0x9UL << XFMC_CTRL_CRDLY_SHIFT) 655 #define XFMC_NAND_CLE_DELAY_11HCLK (0xAUL << XFMC_CTRL_CRDLY_SHIFT) 656 #define XFMC_NAND_CLE_DELAY_12HCLK (0xBUL << XFMC_CTRL_CRDLY_SHIFT) 657 #define XFMC_NAND_CLE_DELAY_13HCLK (0xCUL << XFMC_CTRL_CRDLY_SHIFT) 658 #define XFMC_NAND_CLE_DELAY_14HCLK (0xDUL << XFMC_CTRL_CRDLY_SHIFT) 659 #define XFMC_NAND_CLE_DELAY_15HCLK (0xEUL << XFMC_CTRL_CRDLY_SHIFT) 660 #define XFMC_NAND_CLE_DELAY_16HCLK (0xFUL << XFMC_CTRL_CRDLY_SHIFT) 661 #define IS_XFMC_NAND_CLE_DELAY(DELAY) (0==((DELAY) & (~XFMC_CTRL_CRDLY_MASK))) 662 /** 663 * @} 664 */ 665 666 /** @addtogroup XFMC_ALE_RE_Delay 667 * @{ 668 */ 669 #define XFMC_NAND_ALE_DELAY_1HCLK (0x0UL << XFMC_CTRL_ARDLY_SHIFT) 670 #define XFMC_NAND_ALE_DELAY_2HCLK (0x1UL << XFMC_CTRL_ARDLY_SHIFT) 671 #define XFMC_NAND_ALE_DELAY_3HCLK (0x2UL << XFMC_CTRL_ARDLY_SHIFT) 672 #define XFMC_NAND_ALE_DELAY_4HCLK (0x3UL << XFMC_CTRL_ARDLY_SHIFT) 673 #define XFMC_NAND_ALE_DELAY_5HCLK (0x4UL << XFMC_CTRL_ARDLY_SHIFT) 674 #define XFMC_NAND_ALE_DELAY_6HCLK (0x5UL << XFMC_CTRL_ARDLY_SHIFT) 675 #define XFMC_NAND_ALE_DELAY_7HCLK (0x6UL << XFMC_CTRL_ARDLY_SHIFT) 676 #define XFMC_NAND_ALE_DELAY_8HCLK (0x7UL << XFMC_CTRL_ARDLY_SHIFT) 677 #define XFMC_NAND_ALE_DELAY_9HCLK (0x8UL << XFMC_CTRL_ARDLY_SHIFT) 678 #define XFMC_NAND_ALE_DELAY_10HCLK (0x9UL << XFMC_CTRL_ARDLY_SHIFT) 679 #define XFMC_NAND_ALE_DELAY_11HCLK (0xAUL << XFMC_CTRL_ARDLY_SHIFT) 680 #define XFMC_NAND_ALE_DELAY_12HCLK (0xBUL << XFMC_CTRL_ARDLY_SHIFT) 681 #define XFMC_NAND_ALE_DELAY_13HCLK (0xCUL << XFMC_CTRL_ARDLY_SHIFT) 682 #define XFMC_NAND_ALE_DELAY_14HCLK (0xDUL << XFMC_CTRL_ARDLY_SHIFT) 683 #define XFMC_NAND_ALE_DELAY_15HCLK (0xEUL << XFMC_CTRL_ARDLY_SHIFT) 684 #define XFMC_NAND_ALE_DELAY_16HCLK (0xFUL << XFMC_CTRL_ARDLY_SHIFT) 685 #define IS_XFMC_NAND_ALE_DELAY(DELAY) (0==((DELAY) & (~XFMC_CTRL_ARDLY_MASK))) 686 /** 687 * @} 688 */ 689 690 /** @addtogroup XFMC_ECC_Page_Size 691 * @{ 692 */ 693 #define XFMC_NAND_ECC_PAGE_256BYTES (0x0UL << XFMC_CTRL_ECCPGS_SHIFT) 694 #define XFMC_NAND_ECC_PAGE_512BYTES (0x1UL << XFMC_CTRL_ECCPGS_SHIFT) 695 #define XFMC_NAND_ECC_PAGE_1024BYTES (0x2UL << XFMC_CTRL_ECCPGS_SHIFT) 696 #define XFMC_NAND_ECC_PAGE_2048BYTES (0x3UL << XFMC_CTRL_ECCPGS_SHIFT) 697 #define XFMC_NAND_ECC_PAGE_4096BYTES (0x4UL << XFMC_CTRL_ECCPGS_SHIFT) 698 #define XFMC_NAND_ECC_PAGE_8192BYTES (0x5UL << XFMC_CTRL_ECCPGS_SHIFT) 699 #define IS_XFMC_NAND_ECC_PAGE_SIZE(SIZE) (0==((SIZE) & (~XFMC_CTRL_ECCPGS_MASK))) 700 /** 701 * @} 702 */ 703 704 /** 705 * @} End of NAND_Controller 706 */ 707 708 /** @addtogroup XFMC_StatusFlag 709 * @{ 710 */ 711 #define XFMC_NAND_FLAG_FIFO_EMPTY (XFMC_STS_FIFOEMPT) 712 #define IS_XFMC_NAND_FLAG(FLAG) ((FLAG)==XFMC_NAND_FLAG_FIFO_EMPTY) 713 /** 714 * @} 715 */ 716 717 718 /** @addtogroup XFMC_TimeController 719 * @{ 720 */ 721 722 /** @addtogroup XFMC_Setup_Time 723 * @{ 724 */ 725 #define XFMC_NAND_SETUP_TIME_MIN (0x00000000) 726 #define XFMC_NAND_SETUP_TIME_MAX (0x000000FF) 727 #define XFMC_NAND_SETUP_TIME_DEFAULT (0x000000FC) 728 #define IS_XFMC_NAND_SETUP_TIME(TIME) ((TIME) <= XFMC_NAND_SETUP_TIME_MAX) 729 /** 730 * @} 731 */ 732 733 /** @addtogroup XFMC_Wait_Time 734 * @{ 735 */ 736 #define XFMC_NAND_WAIT_TIME_MIN (0x00000001) 737 #define XFMC_NAND_WAIT_TIME_MAX (0x000000FF) 738 #define XFMC_NAND_WAIT_TIME_DEFAULT (0x000000FC) 739 #define IS_XFMC_NAND_WAIT_TIME(TIME) ( ((TIME) >= XFMC_NAND_WAIT_TIME_MIN) \ 740 && ((TIME) <= XFMC_NAND_WAIT_TIME_MAX) ) 741 /** 742 * @} 743 */ 744 745 /** @addtogroup XFMC_Hold_Time 746 * @{ 747 */ 748 #define XFMC_NAND_HOLD_TIME_MIN (0x00000001) 749 #define XFMC_NAND_HOLD_TIME_MAX (0x000000FF) 750 #define XFMC_NAND_HOLD_TIME_DEFAULT (0x000000FC) 751 #define IS_XFMC_NAND_HOLD_TIME(TIME) ( ((TIME) >= XFMC_NAND_HOLD_TIME_MIN) \ 752 && ((TIME) <= XFMC_NAND_HOLD_TIME_MAX) ) 753 /** 754 * @} 755 */ 756 757 /** @addtogroup XFMC_HiZ_Time 758 * @{ 759 */ 760 #define XFMC_NAND_HIZ_TIME_MIN (0x00000000) 761 #define XFMC_NAND_HIZ_TIME_MAX (0x000000FF) 762 #define XFMC_NAND_HIZ_TIME_DEFAULT (0x000000FC) 763 #define IS_XFMC_NAND_HIZ_TIME(TIME) ((TIME) <= XFMC_NAND_HIZ_TIME_MAX) 764 /** 765 * @} 766 */ 767 768 /** 769 * @} End of XFMC_TimeController 770 */ 771 772 /** 773 * @} 774 */ 775 776 /** 777 * @} 778 */ 779 780 /** @addtogroup XFMC_Exported_Macros 781 * @{ 782 */ 783 784 /** 785 * @} 786 */ 787 788 /** @addtogroup XFMC_Exported_Functions 789 * @{ 790 */ 791 792 void XFMC_DeInitNorSram(XFMC_Bank1_Block *Block); 793 void XFMC_DeInitNand(XFMC_Bank23_Module *Bank); 794 void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct); 795 void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct); 796 void XFMC_InitNorSramStruct(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct); 797 void XFMC_InitNandStruct(XFMC_NandInitType* XFMC_NANDInitStruct); 798 void XFMC_EnableNorSram(XFMC_Bank1_Block *Block, FunctionalState Cmd); 799 void XFMC_EnableNand(XFMC_Bank23_Module *Bank, FunctionalState Cmd); 800 void XFMC_EnableNandEcc(XFMC_Bank23_Module *Bank, FunctionalState Cmd); 801 void XFMC_RestartNandEcc(XFMC_Bank23_Module *Bank); 802 uint32_t XFMC_GetEcc(XFMC_Bank23_Module *Bank); 803 FlagStatus XFMC_GetFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG); 804 void XFMC_ClrFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG); 805 /** 806 * @} 807 */ 808 809 #ifdef __cplusplus 810 } 811 #endif 812 813 #endif /*__N32G45X_XFMC_H__ */ 814 /** 815 * @} 816 */ 817 818 /** 819 * @} 820 */ 821