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Searched refs:XSDPS_CC_SDCLK_FREQ_SEL_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/
A Dxsdps_hw.h206 #define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU macro
A Dxsdps_host.c1086 ClockVal |= (Divisor & XSDPS_CC_SDCLK_FREQ_SEL_MASK) << XSDPS_CC_DIV_SHIFT; in XSdPs_CalcClock()

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