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Searched refs:XSdPs_WriteReg (Results 1 – 3 of 3) sorted by relevance

/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/
A Dxsdps_host.c969 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, in XSdPs_Setup32ADMA2DescTbl()
1042 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, in XSdPs_Setup64ADMA2DescTbl()
1127 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD0_DLL_CTRL, DllCtrl); in XSdPs_DllRstCtrl()
1143 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD1_DLL_CTRL, DllCtrl); in XSdPs_DllRstCtrl()
1163 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl); in XSdPs_DllRstCtrl()
1179 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl); in XSdPs_DllRstCtrl()
1251 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); in XSdPs_ConfigTapDelay()
1254 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); in XSdPs_ConfigTapDelay()
1256 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); in XSdPs_ConfigTapDelay()
1258 XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); in XSdPs_ConfigTapDelay()
[all …]
A Dxsdps_card.c1200 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, in XSdPs_SetupADMA2DescTbl64Bit()
1443 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, in XSdPs_SetupCmd()
1500 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, in XSdPs_SendCmd()
A Dxsdps_hw.h1182 #define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ macro

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