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Searched refs:XUARTPS_IXR_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/zynqmp-a53-dfzu2eg/drivers/
A Ddrv_uart.c57 temp_mask &= (rt_uint32_t)XUARTPS_IXR_MASK; in _uart_set_interrupt_mask()
235 writel(XUARTPS_IXR_MASK, uart->hw_base + XUARTPS_IDR_OFFSET); in zynqmp_uart_configure()
/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/
A Dzynqmp_uart.h133 #define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */ macro

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