Home
last modified time | relevance | path

Searched refs:XUARTPS_MR_OFFSET (Results 1 – 2 of 2) sorted by relevance

/bsp/zynqmp-a53-dfzu2eg/drivers/
A Ddrv_uart.c91 mode_reg = readl(base + XUARTPS_MR_OFFSET); in _uart_baudrate_init()
173 mode_reg = readl(uart->hw_base + XUARTPS_MR_OFFSET); in zynqmp_uart_configure()
226 writel(mode_reg, uart->hw_base + XUARTPS_MR_OFFSET); in zynqmp_uart_configure()
/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/
A Dzynqmp_uart.h33 #define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */ macro

Completed in 11 milliseconds