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Searched refs:XUARTPS_RXWM_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/
A Dzynqmp_uart.h181 #define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */ macro
263 #define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
/bsp/zynqmp-a53-dfzu2eg/drivers/
A Ddrv_uart.c40 RT_ASSERT(trigger_level <= (rt_uint8_t)XUARTPS_RXWM_MASK); in _uart_set_fifo_threshold()
42 reg_triger = ((rt_uint32_t)trigger_level) & (rt_uint32_t)XUARTPS_RXWM_MASK; in _uart_set_fifo_threshold()

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