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Searched refs:XUARTPS_RXWM_OFFSET (Results 1 – 2 of 2) sorted by relevance

/bsp/zynqmp-a53-dfzu2eg/drivers/
A Ddrv_uart.c48 writel(reg_triger, base + XUARTPS_RXWM_OFFSET); in _uart_set_fifo_threshold()
229 writel(0x08U, uart->hw_base + XUARTPS_RXWM_OFFSET); in zynqmp_uart_configure()
/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/
A Dzynqmp_uart.h40 #define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */ macro

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