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Searched refs:XUARTPS_SR_OFFSET (Results 1 – 2 of 2) sorted by relevance

/bsp/zynqmp-a53-dfzu2eg/drivers/
A Ddrv_uart.c271 while ((readl(uart->hw_base + XUARTPS_SR_OFFSET) & in zynqmp_uart_putc()
290 if ((readl(uart->hw_base + XUARTPS_SR_OFFSET) & in zynqmp_uart_getc()
/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/
A Dzynqmp_uart.h43 #define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ macro

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