Searched refs:__I (Results 1 – 25 of 1221) sorted by relevance
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131 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */132 __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */133 __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */134 __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */135 __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */136 __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */137 __I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */138 __I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */139 __I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */140 __I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */[all …]
150 __I uint16_t RESERVED0;152 __I uint16_t RESERVED1;154 __I uint16_t RESERVED2;468 __I uint16_t RESERVED1;511 __I uint16_t RESERVED0;520 __I uint16_t RESERVED1;551 __I uint32_t RESERVED2;586 __I uint32_t RESERVED3;728 __I uint32_t RESERVED4;737 __I uint32_t RESERVED5;[all …]
58 __I uint32_t RV_CTRL_RSVD : 16;70 __I uint32_t ICE_BREAK0_RSVD : 7;72 __I uint32_t ICE_BREAK1_RSVD : 7;76 __I uint32_t TRACE_ADDR_RSVD : 7;78 __I uint32_t TRACE_FIFO_RDATA_RSVD : 7;80 __I uint32_t ICE_STATUS : 8;91 __I uint32_t BIN_CTRL_RSVD : 3;182 __I uint32_t FAULT_STATUS;183 __I uint32_t FAULT_ADDR_ICB;184 __I uint32_t FAULT_ADDR_DTCM;[all …]
319 #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< (GMAC) Network Status Register …326 #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< (GMAC) Interrupt Status Registe…372 #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< (GMAC) Late Collisions Register…377 #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< (GMAC) Frames Received Register…390 #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< (GMAC) Jabbers Received Registe…394 #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< (GMAC) Alignment Errors Registe…396 #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< (GMAC) Receive Overrun Register…414 #define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U) /**< (GMAC) Received LPI Transitions…415 #define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U) /**< (GMAC) Received LPI Time */416 #define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U) /**< (GMAC) Transmit LPI Transitions…[all …]
98 #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< (PIOA) PIO Status Register */101 #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< (PIOA) Output Status Register */108 #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< (PIOA) Pin Data Status Register…111 #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< (PIOA) Interrupt Mask Register …112 #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< (PIOA) Interrupt Status Registe…115 #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< (PIOA) Multi-driver Status Regi…118 #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< (PIOA) Pad Pull-up Status Regis…128 #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< (PIOA) Pad Pull-down Status Reg…131 #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< (PIOA) Output Write Status Regi…137 #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< (PIOA) Edge/Level Status Regist…[all …]
98 #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< (PIOB) PIO Status Register */101 #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< (PIOB) Output Status Register */108 #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< (PIOB) Pin Data Status Register…111 #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< (PIOB) Interrupt Mask Register …112 #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< (PIOB) Interrupt Status Registe…115 #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< (PIOB) Multi-driver Status Regi…118 #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< (PIOB) Pad Pull-up Status Regis…128 #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< (PIOB) Pad Pull-down Status Reg…131 #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< (PIOB) Output Write Status Regi…137 #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< (PIOB) Edge/Level Status Regist…[all …]
98 #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< (PIOC) PIO Status Register */101 #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< (PIOC) Output Status Register */108 #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< (PIOC) Pin Data Status Register…111 #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< (PIOC) Interrupt Mask Register …112 #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< (PIOC) Interrupt Status Registe…115 #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< (PIOC) Multi-driver Status Regi…118 #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< (PIOC) Pad Pull-up Status Regis…128 #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< (PIOC) Pad Pull-down Status Reg…131 #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< (PIOC) Output Write Status Regi…137 #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< (PIOC) Edge/Level Status Regist…[all …]
98 #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< (PIOD) PIO Status Register */101 #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< (PIOD) Output Status Register */108 #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< (PIOD) Pin Data Status Register…111 #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< (PIOD) Interrupt Mask Register …112 #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< (PIOD) Interrupt Status Registe…115 #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< (PIOD) Multi-driver Status Regi…118 #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< (PIOD) Pad Pull-up Status Regis…128 #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< (PIOD) Pad Pull-down Status Reg…131 #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< (PIOD) Output Write Status Regi…137 #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< (PIOD) Edge/Level Status Regist…[all …]
98 #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< (PIOE) PIO Status Register */101 #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< (PIOE) Output Status Register */108 #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< (PIOE) Pin Data Status Register…111 #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< (PIOE) Interrupt Mask Register …112 #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< (PIOE) Interrupt Status Registe…115 #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< (PIOE) Multi-driver Status Regi…118 #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< (PIOE) Pad Pull-up Status Regis…128 #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< (PIOE) Pad Pull-down Status Reg…131 #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< (PIOE) Output Write Status Regi…137 #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< (PIOE) Edge/Level Status Regist…[all …]
462 #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Regist…495 #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register…496 #define REG_USBHS_HSTPIPIMR0 (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register…497 #define REG_USBHS_HSTPIPIMR1 (*(__I uint32_t*)0x400385C4U) /**< (USBHS) Host Pipe Mask Register…498 #define REG_USBHS_HSTPIPIMR2 (*(__I uint32_t*)0x400385C8U) /**< (USBHS) Host Pipe Mask Register…499 #define REG_USBHS_HSTPIPIMR3 (*(__I uint32_t*)0x400385CCU) /**< (USBHS) Host Pipe Mask Register…500 #define REG_USBHS_HSTPIPIMR4 (*(__I uint32_t*)0x400385D0U) /**< (USBHS) Host Pipe Mask Register…501 #define REG_USBHS_HSTPIPIMR5 (*(__I uint32_t*)0x400385D4U) /**< (USBHS) Host Pipe Mask Register…502 #define REG_USBHS_HSTPIPIMR6 (*(__I uint32_t*)0x400385D8U) /**< (USBHS) Host Pipe Mask Register…503 #define REG_USBHS_HSTPIPIMR7 (*(__I uint32_t*)0x400385DCU) /**< (USBHS) Host Pipe Mask Register…[all …]
90 #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< (TC0) Register AB (channel = 0)…91 #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< (TC0) Counter Value (channel = …95 #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel …103 #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< (TC0) Register AB (channel = 0)…104 #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< (TC0) Counter Value (channel = …108 #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< (TC0) Status Register (channel …116 #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< (TC0) Register AB (channel = 0)…117 #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< (TC0) Counter Value (channel = …121 #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< (TC0) Status Register (channel …130 #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< (TC0) QDEC Interrupt Mask Regis…[all …]
90 #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< (TC1) Register AB (channel = 0)…91 #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< (TC1) Counter Value (channel = …95 #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< (TC1) Status Register (channel …103 #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< (TC1) Register AB (channel = 0)…104 #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< (TC1) Counter Value (channel = …108 #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< (TC1) Status Register (channel …116 #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< (TC1) Register AB (channel = 0)…117 #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< (TC1) Counter Value (channel = …121 #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< (TC1) Status Register (channel …130 #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< (TC1) QDEC Interrupt Mask Regis…[all …]
90 #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< (TC2) Register AB (channel = 0)…91 #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< (TC2) Counter Value (channel = …95 #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< (TC2) Status Register (channel …103 #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< (TC2) Register AB (channel = 0)…104 #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< (TC2) Counter Value (channel = …108 #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< (TC2) Status Register (channel …116 #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< (TC2) Register AB (channel = 0)…117 #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< (TC2) Counter Value (channel = …121 #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< (TC2) Status Register (channel …130 #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< (TC2) QDEC Interrupt Mask Regis…[all …]
90 #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< (TC3) Register AB (channel = 0)…91 #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< (TC3) Counter Value (channel = …95 #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< (TC3) Status Register (channel …103 #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< (TC3) Register AB (channel = 0)…104 #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< (TC3) Counter Value (channel = …108 #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< (TC3) Status Register (channel …116 #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< (TC3) Register AB (channel = 0)…117 #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< (TC3) Counter Value (channel = …121 #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< (TC3) Status Register (channel …130 #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< (TC3) QDEC Interrupt Mask Regis…[all …]
395 #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask …409 #define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) /**< (XDMAC) Channel Interrupt Mask …423 #define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) /**< (XDMAC) Channel Interrupt Mask …437 #define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) /**< (XDMAC) Channel Interrupt Mask …451 #define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) /**< (XDMAC) Channel Interrupt Mask …465 #define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) /**< (XDMAC) Channel Interrupt Mask …479 #define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) /**< (XDMAC) Channel Interrupt Mask …729 #define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) /**< (XDMAC) Global Type Register */734 #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< (XDMAC) Global Interrupt Mask R…735 #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< (XDMAC) Global Interrupt Status…[all …]
76 #define REG_DSU_STATUSB (*(__I uint8_t*)0x41002002U) /**< (DSU) Status B */77 #define REG_DSU_STATUSC (*(__I uint8_t*)0x41002003U) /**< (DSU) Status C */84 #define REG_DSU_DID (*(__I uint32_t*)0x41002018U) /**< (DSU) Device Identification */92 #define REG_DSU_ENTRY0 (*(__I uint32_t*)0x41003000U) /**< (DSU) CoreSight ROM Table Entry…93 #define REG_DSU_ENTRY1 (*(__I uint32_t*)0x41003004U) /**< (DSU) CoreSight ROM Table Entry…94 #define REG_DSU_END (*(__I uint32_t*)0x41003008U) /**< (DSU) CoreSight ROM Table End */96 #define REG_DSU_PID4 (*(__I uint32_t*)0x41003FD0U) /**< (DSU) Peripheral Identification…104 #define REG_DSU_CID0 (*(__I uint32_t*)0x41003FF0U) /**< (DSU) Component Identification …105 #define REG_DSU_CID1 (*(__I uint32_t*)0x41003FF4U) /**< (DSU) Component Identification …106 #define REG_DSU_CID2 (*(__I uint32_t*)0x41003FF8U) /**< (DSU) Component Identification …[all …]
131 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */132 __I uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */133 __I uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */134 __I uint32_t HPB1_:1; /*!< bit: 3 HPB1 */135 __I uint32_t HPB0_:1; /*!< bit: 4 HPB0 */136 __I uint32_t HPB2_:1; /*!< bit: 5 HPB2 */137 __I uint32_t LPRAMDMAC_:1; /*!< bit: 6 LPRAMDMAC */138 __I uint32_t DIVAS_:1; /*!< bit: 7 DIVAS */139 __I uint32_t :24; /*!< bit: 8..31 Reserved */170 __I uint32_t PAC_:1; /*!< bit: 0 PAC */[all …]
40 __I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */41 __I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */42 __I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */44 __I uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */45 __I uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */46 __I uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */47 __I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */48 __I uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */49 __I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */50 __I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */[all …]
40 __I uint32_t PID4; /**< JEP_106_BANK */41 __I uint32_t PID5; /**< Unused */42 __I uint32_t PID6; /**< Unused */43 __I uint32_t PID7; /**< Unused */44 __I uint32_t PID0; /**< Chip family LSB, chip major revision */45 __I uint32_t PID1; /**< JEP_106_NO, Chip family MSB */46 __I uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */47 __I uint32_t PID3; /**< Chip minor rev LSB */48 __I uint32_t CID0; /**< Unused */
39 __I uint32_t CAL; /**< Calibration temperature and checksum */40 __I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */41 __I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */42 __I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */44 __I uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */45 __I uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */46 __I uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */48 __I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */49 __I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */51 __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */[all …]
177 __I uint8_t LSR;180 __I uint8_t MSR;275 __I uint32_t STATUS;277 __I uint32_t RX_DATA;281 __I uint32_t MIS;282 __I uint32_t RIS;333 __I uint32_t GPIO_IN;693 __I uint32_t CAR1;694 __I uint32_t CAR2;927 __I uint32_t STATUS;[all …]
278 __I uint32_t LSR;279 __I uint32_t MSR;290 __I uint32_t TFR;292 __I uint32_t USR;293 __I uint32_t TFL;294 __I uint32_t RFL;305 __I uint32_t CPR;306 __I uint32_t UCV;307 __I uint32_t CTR;325 __I uint32_t SR;[all …]
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