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/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/
A Dhc32l19x.h7655 __IO uint32_t HT;
7660 __IO uint32_t LT;
7855 __IO uint32_t CR;
7911 __IO uint32_t CR;
7981 __IO uint32_t CR;
7990 __IO uint32_t CR;
8029 __IO uint32_t CR;
8081 __IO uint32_t SR;
8194 __IO uint32_t CR;
9278 __IO uint32_t TM;
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/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/
A Dhc32l136.h6450 __IO uint32_t HT;
6455 __IO uint32_t LT;
6499 __IO uint32_t CR;
6549 __IO uint32_t CR;
6558 __IO uint32_t CR;
6597 __IO uint32_t CR;
6716 __IO uint32_t CR;
7456 __IO uint32_t TM;
7461 __IO uint32_t CR;
7695 __IO uint8_t CR;
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/bsp/smartfusion2/CMSIS/
A Dm2sxxx.h171 __IO uint8_t LCR;
174 __IO uint8_t MCR;
183 __IO uint8_t SR;
186 __IO uint8_t IEM;
189 __IO uint8_t IIM;
192 __IO uint8_t MM0;
195 __IO uint8_t MM1;
198 __IO uint8_t MM2;
201 __IO uint8_t DFR;
204 __IO uint8_t GFR;
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/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/
A Dfm33lc0xx.h227 __IO uint32_t RSV;
228 __IO uint32_t CR; /*!< Debug Configuration Register */
229 __IO uint32_t HDFR; /*!< HardFault Flag Register*/
278 __IO uint32_t INEN; /*!< Input Enable Register */
279 __IO uint32_t PUEN; /*!< Pull-Up Enable Register */
280 __IO uint32_t ODEN; /*!< Open-Drain Enable Register */
281 __IO uint32_t FCR; /*!< Function Control Register */
282 __IO uint32_t DO; /*!< Data Output Register */
479 __IO uint32_t PDRCR; /*!< PDR Control Register */
480 __IO uint32_t BORCR; /*!< BOR Control Register */
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A Dfm33lg0xx.h150 …__IO uint32_t RDCR; /*!< Flash Read Control Register, …
151 …__IO uint32_t PFCR; /*!< Flash Prefetch Control Register, …
153 …__IO uint32_t ACLOCK1; /*!< Flash Application Code Lock Register1, …
154 …__IO uint32_t ACLOCK2; /*!< Flash Application Code Lock Register2, …
155 …__IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, …
187 …__IO uint32_t CR; /*!< VREFP Control Register, Addres…
188 …__IO uint32_t CFGR; /*!< VREFP Config Register, Addres…
189 …__IO uint32_t ISR; /*!< VREFP Interrupt Status Register, Addres…
190 …__IO uint32_t TR; /*!< VREFP Trim Register, Addres…
400 …__IO uint32_t CR; /*!< ComparatorControl Register 1, Address o…
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/bsp/fm33lc026/libraries/FM/FM33xx/Include/
A Dfm33lc0xx.h227 __IO uint32_t RSV;
228 __IO uint32_t CR; /*!< Debug Configuration Register */
229 __IO uint32_t HDFR; /*!< HardFault Flag Register*/
278 __IO uint32_t INEN; /*!< Input Enable Register */
279 __IO uint32_t PUEN; /*!< Pull-Up Enable Register */
280 __IO uint32_t ODEN; /*!< Open-Drain Enable Register */
281 __IO uint32_t FCR; /*!< Function Control Register */
282 __IO uint32_t DO; /*!< Data Output Register */
479 __IO uint32_t PDRCR; /*!< PDR Control Register */
480 __IO uint32_t BORCR; /*!< BOR Control Register */
[all …]
A Dfm33lg0xx.h150 …__IO uint32_t RDCR; /*!< Flash Read Control Register, …
151 …__IO uint32_t PFCR; /*!< Flash Prefetch Control Register, …
153 …__IO uint32_t ACLOCK1; /*!< Flash Application Code Lock Register1, …
154 …__IO uint32_t ACLOCK2; /*!< Flash Application Code Lock Register2, …
155 …__IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, …
187 …__IO uint32_t CR; /*!< VREFP Control Register, Addres…
188 …__IO uint32_t CFGR; /*!< VREFP Config Register, Addres…
189 …__IO uint32_t ISR; /*!< VREFP Interrupt Status Register, Addres…
190 …__IO uint32_t TR; /*!< VREFP Trim Register, Addres…
400 …__IO uint32_t CR; /*!< ComparatorControl Register 1, Address o…
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/bsp/CME_M7/StdPeriph_Driver/inc/
A Dcmem7.h409 …__IO uint32_t NEG_EDGE : 1; /*!< 1, indicates SPI takes sample at the rise edge …
672 …__IO uint32_t RESET : 1; /*!< TX and RX FIFO are held in an erased state( flu…
957 …__IO uint32_t DATA; /*!< data register. lower bits are significant i…
1408 …__IO uint8_t BRP : 6; /*!< TQ =2 x Txtal1 x (32 x BRP.5 + 16 x BRP.4 + 8 x…
1548 …__IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block…
1625 …__IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register…
1647 …__IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination …
1663 …__IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block…
1740 …__IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register…
1762 …__IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination …
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/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DACM32F0x0.h213 __IO uint32_t RIS;
282 __IO uint32_t MOD;
283 __IO uint32_t CMR;
284 __IO uint32_t SR;
285 __IO uint32_t IR;
286 __IO uint32_t IER;
290 __IO uint32_t OCR;
293 __IO uint32_t ALC;
294 __IO uint32_t ECC;
299 __IO uint32_t RMC;
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/bsp/microchip/same70/bsp/same70b/include/instance/
A Dhsmci.h321 #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< (HSMCI) Mode Register */
322 #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< (HSMCI) Data Timeout Register */
323 #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< (HSMCI) SD/SDIO Card Register */
324 #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< (HSMCI) Argument Register */
326 #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< (HSMCI) Block Register */
340 #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< (HSMCI) Configuration Register …
343 #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0…
344 #define REG_HSMCI_FIFO0 (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0…
345 #define REG_HSMCI_FIFO1 (*(__IO uint32_t*)0x40000204U) /**< (HSMCI) FIFO Memory Aperture0 1…
346 #define REG_HSMCI_FIFO2 (*(__IO uint32_t*)0x40000208U) /**< (HSMCI) FIFO Memory Aperture0 2…
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A Dxdmac.h402 #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< (XDMAC) Channel Block Control R…
403 #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< (XDMAC) Channel Configuration R…
416 #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< (XDMAC) Channel Block Control R…
417 #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< (XDMAC) Channel Configuration R…
430 #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< (XDMAC) Channel Block Control R…
431 #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< (XDMAC) Channel Configuration R…
444 #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< (XDMAC) Channel Block Control R…
445 #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< (XDMAC) Channel Configuration R…
458 #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< (XDMAC) Channel Block Control R…
459 #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< (XDMAC) Channel Configuration R…
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/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DACM32F4.h176 __IO uint32_t SR;
203 __IO uint32_t WP;
204 __IO uint32_t IE;
205 __IO uint32_t SR;
214 __IO uint32_t CR;
228 __IO uint32_t SR;
252 __IO uint32_t PR;
254 __IO uint32_t SR;
263 __IO uint32_t DR;
266 __IO uint32_t FR;
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/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/
A Dmb9b610t.h11561 __IO uint16_t PRLL;
11563 __IO uint16_t PRLH;
11565 __IO uint16_t TMR;
11588 __IO uint16_t PCSR;
11590 __IO uint16_t PDUT;
11592 __IO uint16_t TMR;
11615 __IO uint16_t PCSR;
11617 __IO uint16_t TMR;
11641 __IO uint16_t DTBF;
11728 __IO uint16_t QPCR;
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A Dmb9b610s.h11353 __IO uint16_t PRLL;
11355 __IO uint16_t PRLH;
11357 __IO uint16_t TMR;
11380 __IO uint16_t PCSR;
11382 __IO uint16_t PDUT;
11384 __IO uint16_t TMR;
11407 __IO uint16_t PCSR;
11409 __IO uint16_t TMR;
11433 __IO uint16_t DTBF;
11520 __IO uint16_t QPCR;
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/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/
A Dht32f1xxxx_01.h254 typedef __IO s64 vs64;
255 typedef __IO s32 vs32;
256 typedef __IO s16 vs16;
257 typedef __IO s8 vs8;
274 typedef __IO u64 vu64;
275 typedef __IO u32 vu32;
276 typedef __IO u16 vu16;
277 typedef __IO u8 vu8;
394 …__IO uint32_t DR; /*!< 0x000 Data Register …
395 …__IO uint32_t RBR; /*!< 0x000 Receive Buffer Register …
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/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/
A Dmb9bf506r.h7226 __IO uint16_t PRLL;
7228 __IO uint16_t PRLH;
7230 __IO uint16_t TMR;
7253 __IO uint16_t PCSR;
7255 __IO uint16_t PDUT;
7257 __IO uint16_t TMR;
7280 __IO uint16_t PCSR;
7282 __IO uint16_t TMR;
7306 __IO uint16_t DTBF;
7367 __IO uint16_t QPCR;
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/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Defpga_template_reg_defs.h30 #ifndef __IO
31 #define __IO volatile macro
48 __IO uint32_t tcdm_ctl_p0;
59 __IO uint32_t tcdm_ctl_p1;
70 __IO uint32_t tcdm_ctl_p2;
81 __IO uint32_t tcdm_ctl_p3;
92 __IO uint32_t m0_m0_control;
193 __IO uint32_t m0_m0_clken;
201 __IO uint32_t m0_m1_clken;
209 __IO uint32_t m1_m0_clken;
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A Dadv_timer_unit_reg_defs.h30 #ifndef __IO
31 #define __IO volatile macro
48 __IO uint32_t timer_0_cmd_register;
51 __IO uint32_t stop_command : 1;
54 __IO uint32_t arm_command : 1;
55 __IO uint32_t reserved1 : 27;
65 __IO uint32_t clock_sel : 1;
67 __IO uint32_t reserved2 : 3;
69 __IO uint32_t reserved1 : 8;
88 __IO uint32_t reserved1 : 13;
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A Dhal_apb_interrupt_cntrl_reg_defs.h30 #ifndef __IO
31 #define __IO volatile macro
48 __IO uint32_t reg_mask;
66 __IO uint32_t reg_mask_set;
84 __IO uint32_t reg_mask_clear;
102 __IO uint32_t reg_int;
120 __IO uint32_t reg_int_set;
138 __IO uint32_t reg_int_clear;
156 __IO uint32_t reg_ack;
174 __IO uint32_t reg_ack_set;
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A Dhal_apb_i2cs_reg_defs.h30 #ifndef __IO
31 #define __IO volatile macro
48 __IO uint32_t i2cs_dev_address;
50 __IO uint32_t slave_addr : 7;
51 __IO uint32_t reserved : 1;
57 __IO uint32_t i2cs_enable;
59 __IO uint32_t ip_enable : 1;
60 __IO uint32_t reserved : 7;
68 __IO uint32_t deb_len : 8;
91 __IO uint32_t i2cs_msg_i2c_apb;
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/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/
A Dmb9b560r.h295 __IO uint32_t DRQSEL;
8634 __IO uint32_t FSTR;
9632 __IO uint8_t STC;
9659 __IO uint8_t STC;
9684 __IO uint8_t STC;
9708 __IO uint8_t STC;
10965 __IO uint32_t ADE;
11593 __IO uint8_t CMD;
11595 __IO uint8_t CFG;
12530 __IO uint32_t EST;
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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_i2c.h63 __IO u32 IC_CON;
67 __IO u32 IC_TAR;
71 __IO u32 IC_SAR;
212 __IO u32 RESERVED3;
251 __IO u32 IC_CON;
252 __IO u32 IC_TAR;
253 __IO u32 IC_SAR;
265 __IO u32 IC_RX_TL;
266 __IO u32 IC_TX_TL;
280 __IO u32 IC_TXFLR;
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/bsp/Vango/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/
A Dlib_LoadNVR.h115 #define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x80C48)
116 #define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x80C6C)
117 #define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x80C00)
118 #define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x80C24)
121 #define NVR_RTC1_P4 (__IO uint32_t *)(0x80800)
122 #define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x80804)
123 #define NVR_RTC2_P4 (__IO uint32_t *)(0x80808)
124 #define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x8080C)
126 #define NVR_RTC1_ACK0 (__IO uint32_t *)(0x80810)
127 #define NVR_RTC1_ACK1 (__IO uint32_t *)(0x80814)
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/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_usb_ll_driver.c83 __IO uint8_t POWER;
98 __IO uint16_t INTRTX;
121 __IO uint16_t INTRRX;
229 __IO uint8_t INDEX;
230 __IO uint8_t TESTMODE;
247 __IO uint8_t CSR0L;
717 __IO uint8_t VPLEN;
718 __IO uint8_t HS_EOF1;
719 __IO uint8_t FS_EOF1;
720 __IO uint8_t LS_EOF1;
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/bsp/microchip/saml10/bsp/include/instance/
A Dtram.h114 #define REG_TRAM_CTRLA (*(__IO uint8_t*)0x42003400U) /**< (TRAM) Control */
123 #define REG_TRAM_RAM (*(__IO uint32_t*)0x42003500U) /**< (TRAM) TrustRAM */
124 #define REG_TRAM_RAM0 (*(__IO uint32_t*)0x42003500U) /**< (TRAM) TrustRAM 0 */
125 #define REG_TRAM_RAM1 (*(__IO uint32_t*)0x42003504U) /**< (TRAM) TrustRAM 1 */
126 #define REG_TRAM_RAM2 (*(__IO uint32_t*)0x42003508U) /**< (TRAM) TrustRAM 2 */
127 #define REG_TRAM_RAM3 (*(__IO uint32_t*)0x4200350CU) /**< (TRAM) TrustRAM 3 */
128 #define REG_TRAM_RAM4 (*(__IO uint32_t*)0x42003510U) /**< (TRAM) TrustRAM 4 */
129 #define REG_TRAM_RAM5 (*(__IO uint32_t*)0x42003514U) /**< (TRAM) TrustRAM 5 */
130 #define REG_TRAM_RAM6 (*(__IO uint32_t*)0x42003518U) /**< (TRAM) TrustRAM 6 */
131 #define REG_TRAM_RAM7 (*(__IO uint32_t*)0x4200351CU) /**< (TRAM) TrustRAM 7 */
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