Searched refs:__O (Results 1 – 25 of 963) sorted by relevance
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473 #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Registe…484 #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register …485 #define REG_USBHS_HSTPIPIFR0 (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register …486 #define REG_USBHS_HSTPIPIFR1 (*(__O uint32_t*)0x40038594U) /**< (USBHS) Host Pipe Set Register …487 #define REG_USBHS_HSTPIPIFR2 (*(__O uint32_t*)0x40038598U) /**< (USBHS) Host Pipe Set Register …488 #define REG_USBHS_HSTPIPIFR3 (*(__O uint32_t*)0x4003859CU) /**< (USBHS) Host Pipe Set Register …489 #define REG_USBHS_HSTPIPIFR4 (*(__O uint32_t*)0x400385A0U) /**< (USBHS) Host Pipe Set Register …490 #define REG_USBHS_HSTPIPIFR5 (*(__O uint32_t*)0x400385A4U) /**< (USBHS) Host Pipe Set Register …491 #define REG_USBHS_HSTPIPIFR6 (*(__O uint32_t*)0x400385A8U) /**< (USBHS) Host Pipe Set Register …492 #define REG_USBHS_HSTPIPIFR7 (*(__O uint32_t*)0x400385ACU) /**< (USBHS) Host Pipe Set Register …[all …]
214 #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< (PWM0) PWM Enable Register */215 #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< (PWM0) PWM Disable Register */217 #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< (PWM0) PWM Interrupt Enable Reg…218 #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< (PWM0) PWM Interrupt Disable Re…222 #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< (PWM0) PWM DMA Register */226 #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< (PWM0) PWM Interrupt Enable Reg…227 #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< (PWM0) PWM Interrupt Disable Re…232 #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< (PWM0) PWM Output Selection Set…233 #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< (PWM0) PWM Output Selection Cle…238 #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< (PWM0) PWM Fault Clear Register…[all …]
214 #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< (PWM1) PWM Enable Register */215 #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< (PWM1) PWM Disable Register */217 #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< (PWM1) PWM Interrupt Enable Reg…218 #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< (PWM1) PWM Interrupt Disable Re…222 #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< (PWM1) PWM DMA Register */226 #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< (PWM1) PWM Interrupt Enable Reg…227 #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< (PWM1) PWM Interrupt Disable Re…232 #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< (PWM1) PWM Output Selection Set…233 #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< (PWM1) PWM Output Selection Cle…238 #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< (PWM1) PWM Fault Clear Register…[all …]
96 #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< (PIOA) PIO Enable Register */97 #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< (PIOA) PIO Disable Register */99 #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< (PIOA) Output Enable Register */100 #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< (PIOA) Output Disable Register …105 #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< (PIOA) Set Output Data Register…116 #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< (PIOA) Pull-up Disable Register…117 #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< (PIOA) Pull-up Enable Register …129 #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< (PIOA) Output Write Enable */130 #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< (PIOA) Output Write Disable */135 #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< (PIOA) Edge Select Register */[all …]
96 #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< (PIOB) PIO Enable Register */97 #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< (PIOB) PIO Disable Register */99 #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< (PIOB) Output Enable Register */100 #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< (PIOB) Output Disable Register …105 #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< (PIOB) Set Output Data Register…116 #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< (PIOB) Pull-up Disable Register…117 #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< (PIOB) Pull-up Enable Register …129 #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< (PIOB) Output Write Enable */130 #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< (PIOB) Output Write Disable */135 #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< (PIOB) Edge Select Register */[all …]
96 #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< (PIOC) PIO Enable Register */97 #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< (PIOC) PIO Disable Register */99 #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< (PIOC) Output Enable Register */100 #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< (PIOC) Output Disable Register …105 #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< (PIOC) Set Output Data Register…116 #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< (PIOC) Pull-up Disable Register…117 #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< (PIOC) Pull-up Enable Register …129 #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< (PIOC) Output Write Enable */130 #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< (PIOC) Output Write Disable */135 #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< (PIOC) Edge Select Register */[all …]
96 #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< (PIOD) PIO Enable Register */97 #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< (PIOD) PIO Disable Register */99 #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< (PIOD) Output Enable Register */100 #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< (PIOD) Output Disable Register …105 #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< (PIOD) Set Output Data Register…116 #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< (PIOD) Pull-up Disable Register…117 #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< (PIOD) Pull-up Enable Register …129 #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< (PIOD) Output Write Enable */130 #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< (PIOD) Output Write Disable */135 #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< (PIOD) Edge Select Register */[all …]
96 #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< (PIOE) PIO Enable Register */97 #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< (PIOE) PIO Disable Register */99 #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< (PIOE) Output Enable Register */100 #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< (PIOE) Output Disable Register …105 #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< (PIOE) Set Output Data Register…116 #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< (PIOE) Pull-up Disable Register…117 #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< (PIOE) Pull-up Enable Register …129 #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< (PIOE) Output Write Enable */130 #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< (PIOE) Output Write Disable */135 #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< (PIOE) Edge Select Register */[all …]
88 #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< (AES) Control Register */94 #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register */95 #define REG_AES_KEYWR0 (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register 0 */96 #define REG_AES_KEYWR1 (*(__O uint32_t*)0x4006C024U) /**< (AES) Key Word Register 1 */97 #define REG_AES_KEYWR2 (*(__O uint32_t*)0x4006C028U) /**< (AES) Key Word Register 2 */98 #define REG_AES_KEYWR3 (*(__O uint32_t*)0x4006C02CU) /**< (AES) Key Word Register 3 */99 #define REG_AES_KEYWR4 (*(__O uint32_t*)0x4006C030U) /**< (AES) Key Word Register 4 */100 #define REG_AES_KEYWR5 (*(__O uint32_t*)0x4006C034U) /**< (AES) Key Word Register 5 */101 #define REG_AES_KEYWR6 (*(__O uint32_t*)0x4006C038U) /**< (AES) Key Word Register 6 */102 #define REG_AES_KEYWR7 (*(__O uint32_t*)0x4006C03CU) /**< (AES) Key Word Register 7 */[all …]
60 #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< (ICM) Control Register */62 #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< (ICM) Interrupt Enable Register…63 #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< (ICM) Interrupt Disable Registe…69 #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0…70 #define REG_ICM_UIHVAL0 (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0…71 #define REG_ICM_UIHVAL1 (*(__O uint32_t*)0x4004803CU) /**< (ICM) User Initial Hash Value 0…72 #define REG_ICM_UIHVAL2 (*(__O uint32_t*)0x40048040U) /**< (ICM) User Initial Hash Value 0…73 #define REG_ICM_UIHVAL3 (*(__O uint32_t*)0x40048044U) /**< (ICM) User Initial Hash Value 0…74 #define REG_ICM_UIHVAL4 (*(__O uint32_t*)0x40048048U) /**< (ICM) User Initial Hash Value 0…75 #define REG_ICM_UIHVAL5 (*(__O uint32_t*)0x4004804CU) /**< (ICM) User Initial Hash Value 0…[all …]
393 #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< (XDMAC) Channel Interrupt Enabl…407 #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< (XDMAC) Channel Interrupt Enabl…421 #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< (XDMAC) Channel Interrupt Enabl…435 #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< (XDMAC) Channel Interrupt Enabl…449 #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< (XDMAC) Channel Interrupt Enabl…463 #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< (XDMAC) Channel Interrupt Enabl…477 #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< (XDMAC) Channel Interrupt Enabl…732 #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< (XDMAC) Global Interrupt Enable…733 #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< (XDMAC) Global Interrupt Disabl…736 #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< (XDMAC) Global Channel Enable R…[all …]
85 #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< (PMC) System Clock Enable Regis…86 #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< (PMC) System Clock Disable Regi…88 #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< (PMC) Peripheral Clock Enable R…89 #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< (PMC) Peripheral Clock Disable …106 #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< (PMC) Interrupt Enable Register…107 #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< (PMC) Interrupt Disable Registe…112 #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< (PMC) Fault Output Clear Regist…120 #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< (PMC) SleepWalking Enable Regis…121 #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< (PMC) SleepWalking Disable Regi…125 #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< (PMC) SleepWalking Enable Regis…[all …]
56 #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< (DACC) Control Register */59 #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< (DACC) Channel Enable Register …60 #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< (DACC) Channel Disable Register…62 #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register…63 #define REG_DACC_CDR0 (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register…64 #define REG_DACC_CDR1 (*(__O uint32_t*)0x40040020U) /**< (DACC) Conversion Data Register…65 #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< (DACC) Interrupt Enable Registe…66 #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< (DACC) Interrupt Disable Regist…
87 #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< (TC0) Channel Control Register …96 #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< (TC0) Interrupt Enable Register…97 #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< (TC0) Interrupt Disable Registe…100 #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< (TC0) Channel Control Register …109 #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< (TC0) Interrupt Enable Register…110 #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< (TC0) Interrupt Disable Registe…113 #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< (TC0) Channel Control Register …122 #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< (TC0) Interrupt Enable Register…126 #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< (TC0) Block Control Register */128 #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< (TC0) QDEC Interrupt Enable Reg…[all …]
87 #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< (TC1) Channel Control Register …96 #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< (TC1) Interrupt Enable Register…97 #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< (TC1) Interrupt Disable Registe…100 #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< (TC1) Channel Control Register …109 #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< (TC1) Interrupt Enable Register…110 #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< (TC1) Interrupt Disable Registe…113 #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< (TC1) Channel Control Register …122 #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< (TC1) Interrupt Enable Register…126 #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< (TC1) Block Control Register */128 #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< (TC1) QDEC Interrupt Enable Reg…[all …]
87 #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< (TC2) Channel Control Register …96 #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< (TC2) Interrupt Enable Register…97 #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< (TC2) Interrupt Disable Registe…100 #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< (TC2) Channel Control Register …109 #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< (TC2) Interrupt Enable Register…110 #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< (TC2) Interrupt Disable Registe…113 #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< (TC2) Channel Control Register …122 #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< (TC2) Interrupt Enable Register…126 #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< (TC2) Block Control Register */128 #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< (TC2) QDEC Interrupt Enable Reg…[all …]
87 #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< (TC3) Channel Control Register …96 #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< (TC3) Interrupt Enable Register…97 #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< (TC3) Interrupt Disable Registe…100 #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< (TC3) Channel Control Register …109 #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< (TC3) Interrupt Enable Register…110 #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< (TC3) Interrupt Disable Registe…113 #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< (TC3) Channel Control Register …122 #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< (TC3) Interrupt Enable Register…126 #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< (TC3) Block Control Register */128 #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< (TC3) QDEC Interrupt Enable Reg…[all …]
50 #define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< (I2SC0) Control Register */53 #define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< (I2SC0) Status Clear Register */54 #define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< (I2SC0) Status Set Register */55 #define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< (I2SC0) Interrupt Enable Regist…56 #define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< (I2SC0) Interrupt Disable Regis…59 #define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< (I2SC0) Transmitter Holding Reg…
50 #define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) /**< (I2SC1) Control Register */53 #define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) /**< (I2SC1) Status Clear Register */54 #define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) /**< (I2SC1) Status Set Register */55 #define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) /**< (I2SC1) Interrupt Enable Regist…56 #define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) /**< (I2SC1) Interrupt Disable Regis…59 #define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) /**< (I2SC1) Transmitter Holding Reg…
56 #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< (QSPI) Control Register */59 #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< (QSPI) Transmit Data Register */61 #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< (QSPI) Interrupt Enable Registe…62 #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< (QSPI) Interrupt Disable Regist…69 #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< (QSPI) Scrambling Key Register …
74 #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< (ISI) ISI Control Register */76 #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< (ISI) ISI Interrupt Enable Regi…77 #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< (ISI) ISI Interrupt Disable Reg…79 #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< (ISI) DMA Channel Enable Regist…80 #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< (ISI) DMA Channel Disable Regis…
51 #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< (UART0) Control Register */53 #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< (UART0) Interrupt Enable Regist…54 #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< (UART0) Interrupt Disable Regis…58 #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< (UART0) Transmit Holding Regist…
51 #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< (UART1) Control Register */53 #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< (UART1) Interrupt Enable Regist…54 #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< (UART1) Interrupt Disable Regis…58 #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< (UART1) Transmit Holding Regist…
331 __O uint32_t L2_ADDRESS;333 __O uint32_t CONFIG;337 __O uint32_t LUT;339 __O uint32_t SPECIAL;343 __O uint32_t DIRECTION;347 __O uint32_t TCDM_ADDR;348 __O uint32_t L2_ADDR;349 __O uint32_t CONF_REG;351 __O uint32_t LUT_REG;354 __O uint32_t MODE_REG;[all …]
33 __O rt_uint32_t response0;34 __O rt_uint32_t response1;35 __O rt_uint32_t response2;36 __O rt_uint32_t response3;40 __O rt_uint32_t rx_fifo;
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