Home
last modified time | relevance | path

Searched refs:__OM (Results 1 – 25 of 576) sorted by relevance

12345678910>>...24

/bsp/apm32/libraries/APM32S10x_Library/Device/Geehy/APM32S10x/Include/
A Dapm32s10x.h224 #ifndef __OM
225 #define __OM __O macro
615 __OM uint32_t BSC;
657 __OM uint32_t BC;
978 __OM uint32_t KEY;
989 __OM uint32_t OBKEY;
1041 __OM uint32_t ADDR;
1234 __OM uint32_t ALRH;
1246 __OM uint32_t ALRL;
1975 __OM uint32_t CEG;
[all …]
/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Include/
A Dapm32f0xx.h361 #ifndef __OM
362 #define __OM __O macro
1140 __OM uint32_t TXDATA;
1430 __OM uint32_t SWTRG;
2504 __OM uint32_t KEY;
2515 __OM uint32_t OBKEY;
2568 __OM uint32_t ADDR;
2780 __OM uint32_t BSC;
2886 __OM uint32_t BR;
3138 __OM uint32_t KEY;
[all …]
/bsp/apm32/libraries/APM32E10x_Library/Device/Geehy/APM32E10x/Include/
A Dapm32e10x.h231 #ifndef __OM
232 #define __OM __O macro
643 __OM uint32_t BSC;
685 __OM uint32_t BC;
1020 __OM uint32_t KEY;
1031 __OM uint32_t OBKEY;
1083 __OM uint32_t ADDR;
1273 __OM uint32_t ALRH;
1285 __OM uint32_t ALRL;
2014 __OM uint32_t CEG;
[all …]
/bsp/apm32/libraries/APM32F4xx_Library/Device/Geehy/APM32F4xx/Include/
A Dapm32f4xx.h323 #ifndef __OM
324 #define __OM __O macro
518 __OM uint16_t BSCL;
543 __OM uint16_t BSCH;
1374 __OM uint32_t KEY;
1488 __OM uint32_t CTRL;
2020 __OM uint32_t CEG;
6557 __OM uint32_t K0L;
6568 __OM uint32_t K0R;
6579 __OM uint32_t K1L;
[all …]
/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/
A Dapm32f10x.h351 #ifndef __OM
352 #define __OM __O macro
818 __OM uint32_t BSC;
860 __OM uint32_t BC;
1208 __OM uint32_t KEY;
1219 __OM uint32_t OBKEY;
1271 __OM uint32_t ADDR;
1464 __OM uint32_t ALRH;
1476 __OM uint32_t ALRL;
2205 __OM uint32_t CEG;
[all …]
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G074.h88 #define __OM __O macro
2382 … __OM uint32_t CLROC1FL : 1; /*!< [10..10] Channel n overcurrent lower limit detection flag 1
2385 … __OM uint32_t CLROC2FL : 1; /*!< [12..12] Channel n overcurrent lower limit detection flag 2
2389 … __OM uint32_t CLROWD0N : 1; /*!< [16..16] Channel n overcurrent detection window notification
2391 … __OM uint32_t CLROWD1N : 1; /*!< [17..17] Channel n overcurrent detection window notification
2393 … __OM uint32_t CLROWD2N : 1; /*!< [18..18] Channel n overcurrent detection window notification
2395 … __OM uint32_t CLROWD3N : 1; /*!< [19..19] Channel n overcurrent detection window notification
13023 … __OM uint32_t PERIERR_CLR0; /*!< (@ 0x00000078) Peripheral Error Event Status Clear Register
13096 … __OM uint32_t PERIERR_CLR1; /*!< (@ 0x0000007C) Peripheral Error Event Status Clear Register
13684 … __OM uint32_t PERIERR_CLR2; /*!< (@ 0x00000130) Peripheral Error Event Status Clear Register
[all …]
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6M3AH.h67 #define __OM __O macro
2146 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2213 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2240 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
6220 … __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
6222 … __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
6841 … __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
10255 … __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
11650 … __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only
11655 … __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the
[all …]
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h108 #define __OM __O macro
2683 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2750 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2777 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
9168 … __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF
9184 … __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software
9939 … __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
9941 … __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
10564 … __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
14267 … __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
[all …]
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h108 #define __OM __O macro
2683 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2750 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2777 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
9168 … __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF
9184 … __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software
9939 … __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
9941 … __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
10564 … __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
14267 … __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
[all …]
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h108 #define __OM __O macro
2683 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2750 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2777 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
9168 … __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF
9184 … __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software
9939 … __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
9941 … __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
10564 … __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
14267 … __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
[all …]
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h108 #define __OM __O macro
2683 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2750 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2777 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
9168 … __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF
9184 … __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software
9939 … __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
9941 … __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
10564 … __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
14267 … __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
[all …]
/bsp/ck802/libraries/common/usart/
A Ddw_usart.h84 __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */
93 __OM uint32_t FCR; /* Offset: 0x008 ( /W) FIFO control register */
102 __OM uint32_t RFW; /* Offset: 0x078 ( /W) receive FIFO write */
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA8D1BH.h74 #define __OM __O macro
2496 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2510 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2524 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2538 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2562 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2589 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
7095 … __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
7097 … __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
7754 … __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
[all …]
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA8D1BH.h74 #define __OM __O macro
2496 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2510 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2524 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2538 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2562 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2589 … __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
7095 … __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
7097 … __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
7754 … __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/renesas/ra6m4-iot/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/renesas/ra4e2-eco/ra/arm/CMSIS_6/CMSIS/Core/Include/
A Dcore_cm7.h254 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
502 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
507 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
508 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
509 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1047 __OM union
1049 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
1050 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
1051 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
1061 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */
[all …]
/bsp/renesas/ra6e2-fpb/ra/arm/CMSIS_6/CMSIS/Core/Include/
A Dcore_cm7.h254 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
502 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
507 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
508 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
509 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1047 __OM union
1049 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
1050 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
1051 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
1061 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */
[all …]
/bsp/renesas/ra4m2-eco/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
/bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]

Completed in 6289 milliseconds

12345678910>>...24