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/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/
A Dhpm_esc_regs.h16 __R uint8_t FMMU_NUM; /* 0x4: FMMU supported */
18 __R uint8_t RAM_SIZE; /* 0x6: RAM Size */
19 __R uint8_t PORT_DESC; /* 0x7: Port Descriptor */
21 __R uint8_t RESERVED0[6]; /* 0xA - 0xF: Reserved */
24 __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */
97 __R uint16_t LENGTH; /* 0x604: Length */
102 __R uint8_t TYPE; /* 0x60B: Type */
103 __R uint8_t ACTIVATE; /* 0x60C: Activate */
109 __R uint16_t LENGTH; /* 0x802: Length */
110 __R uint8_t CONTROL; /* 0x804: Control */
[all …]
A Dhpm_tsw_regs.h13 __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */
111 __R uint32_t CENTRAL_QCI_AENTRY_OCYCLETM; /* 0x21A8: */
112 __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_L;/* 0x21AC: */
113 __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_H;/* 0x21B0: */
243 __R uint32_t CPU_PORT_MONITOR_PARAM; /* 0x1800C: */
280 __R uint32_t MAC_VER; /* 0x20000: */
284 __R uint32_t MAC_TX_FRAMES; /* 0x20010: */
285 __R uint32_t MAC_RX_FRAMES; /* 0x20014: */
286 __R uint32_t MAC_TX_OCTETS; /* 0x20018: */
287 __R uint32_t MAC_RX_OCTETS; /* 0x2001C: */
[all …]
A Dhpm_plic_regs.h15 __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */
17 __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */
18 __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */
19 __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */
20 …__R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and ta…
21 __R uint32_t INFO; /* 0x1104: Version and the maximum priority */
22 __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */
25 __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */
27 __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */
31 __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */
[all …]
A Dhpm_lobs_regs.h14 __R uint8_t RESERVED0[8]; /* 0x4 - 0xB: Reserved */
19 __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */
23 __R uint8_t RESERVED2[4]; /* 0x2C - 0x2F: Reserved */
24 __R uint32_t FIFOSTATE; /* 0x30: Fifo State Register */
26 __R uint8_t RESERVED3[24]; /* 0x38 - 0x4F: Reserved */
30 __R uint8_t RESERVED4[4]; /* 0x5C - 0x5F: Reserved */
32 __R uint8_t RESERVED5[52]; /* 0x64 - 0x97: Reserved */
34 __R uint8_t RESERVED6[100]; /* 0x9C - 0xFF: Reserved */
40 __R uint8_t RESERVED0[16]; /* 0x110 - 0x11F: Reserved */
42 __R uint8_t RESERVED1[12]; /* 0x124 - 0x12F: Reserved */
[all …]
A Dhpm_vsc_regs.h16 __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
18 __R uint8_t RESERVED1[4]; /* 0x14 - 0x17: Reserved */
20 __R uint8_t RESERVED2[4]; /* 0x1C - 0x1F: Reserved */
37 __R uint8_t RESERVED3[160]; /* 0x60 - 0xFF: Reserved */
38 __R uint32_t ID_POSEDGE; /* 0x100: posedge order Id value */
39 __R uint32_t IQ_POSEDGE; /* 0x104: posedge order Iq value */
40 __R uint32_t ID_NEGEDGE; /* 0x108: negedge order Id value */
41 __R uint32_t IQ_NEGEDGE; /* 0x10C: negedge order Iq value */
43 __R uint32_t BETA_POSEDGE; /* 0x114: posedge order beta value */
46 __R uint32_t TIMESTAMP_LOCKED; /* 0x120: timestamp_locked */
[all …]
A Dhpm_qeiv2_regs.h27 __R uint32_t PH; /* 0x34: Phase counter */
29 __R uint32_t TMR; /* 0x3C: Timer counter */
42 __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */
44 __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */
46 __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */
47 __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */
48 __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */
53 __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */
55 __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */
66 __R uint32_t TIMESTAMP; /* 0x1E0: timestamp */
[all …]
A Dhpm_plic_sw_regs.h13 __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */
15 __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */
17 __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_plic_regs.h15 __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */
17 __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */
18 __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */
19 __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */
20 …__R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and ta…
21 __R uint32_t INFO; /* 0x1104: Version and the maximum priority */
22 __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */
25 __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */
27 __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */
31 __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */
[all …]
A Dhpm_plic_sw_regs.h13 __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */
15 __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */
17 __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/
A Dhpm_plic_regs.h15 __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */
17 __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */
18 __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */
19 __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */
20 …__R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and ta…
21 __R uint32_t INFO; /* 0x1104: Version and the maximum priority */
22 __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */
25 __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */
27 __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */
31 __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */
[all …]
A Dhpm_plic_sw_regs.h13 __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */
15 __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */
17 __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/
A Dhpm_plic_regs.h15 __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */
17 __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */
18 __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */
19 __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */
20 …__R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and ta…
21 __R uint32_t INFO; /* 0x1104: Version and the maximum priority */
22 __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */
25 __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */
27 __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */
31 __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */
[all …]
A Dhpm_gpu_regs.h14 __R uint32_t AQHILDLE; /* 0x4: idle status register */
15 __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */
18 __R uint8_t RESERVED1[12]; /* 0x18 - 0x23: Reserved */
20 __R uint32_t GCCHIPDATE; /* 0x28: chip date register */
21 __R uint8_t RESERVED2[108]; /* 0x2C - 0x97: Reserved */
23 __R uint8_t RESERVED3[12]; /* 0x9C - 0xA7: Reserved */
25 __R uint8_t RESERVED4[84]; /* 0xAC - 0xFF: Reserved */
29 __R uint8_t RESERVED5[756]; /* 0x10C - 0x3FF: Reserved */
31 __R uint8_t RESERVED6[16]; /* 0x404 - 0x413: Reserved */
33 __R uint8_t RESERVED7[20]; /* 0x418 - 0x42B: Reserved */
[all …]
A Dhpm_mipi_csi_phy_regs.h19 __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */
24 __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */
28 __R uint8_t RESERVED2[8]; /* 0x3C - 0x43: Reserved */
32 __R uint8_t RESERVED3[32]; /* 0x50 - 0x6F: Reserved */
36 __R uint32_t BIST_TEST3; /* 0x7C: bist test control */
37 __R uint8_t RESERVED4[32]; /* 0x80 - 0x9F: Reserved */
40 __R uint32_t BURN_IN_TEST2; /* 0xA8: bist test control */
41 __R uint8_t RESERVED5[4]; /* 0xAC - 0xAF: Reserved */
45 __R uint8_t RESERVED6[8]; /* 0xBC - 0xC3: Reserved */
47 __R uint8_t RESERVED7[8]; /* 0xC8 - 0xCF: Reserved */
[all …]
A Dhpm_smix_regs.h13 __R uint32_t DMAC_ID; /* 0x0: DMAC_ID Register */
17 __R uint8_t RESERVED0[16]; /* 0x10 - 0x1F: Reserved */
20 __R uint8_t RESERVED1[12]; /* 0x28 - 0x33: Reserved */
22 __R uint8_t RESERVED2[8]; /* 0x38 - 0x3F: Reserved */
27 __R uint8_t RESERVED0[4]; /* 0x4C - 0x4F: Reserved */
29 __R uint8_t RESERVED1[4]; /* 0x54 - 0x57: Reserved */
31 __R uint8_t RESERVED2[4]; /* 0x5C - 0x5F: Reserved */
33 __R uint8_t RESERVED3[1152]; /* 0x380 - 0x7FF: Reserved */
37 __R uint8_t RESERVED4[52]; /* 0x80C - 0x83F: Reserved */
46 __R uint8_t RESERVED0[4]; /* 0x85C - 0x85F: Reserved */
[all …]
A Dhpm_plic_sw_regs.h13 __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */
15 __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */
17 __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/
A Dhpm_plic_regs.h15 __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */
17 __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */
18 __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */
19 __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */
20 …__R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and ta…
21 __R uint32_t INFO; /* 0x1104: Version and the maximum priority */
22 __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */
25 __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */
27 __R uint8_t RESERVED4[2088832]; /* 0x2080 - 0x1FFFFF: Reserved */
31 __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */
[all …]
A Dhpm_mmc_regs.h44 __R uint8_t RESERVED0[4]; /* 0x7C - 0x7F: Reserved */
50 __R uint8_t RESERVED1[12]; /* 0x94 - 0x9F: Reserved */
58 __R uint8_t RESERVED2[36]; /* 0xDC - 0xFF: Reserved */
65 __R uint8_t RESERVED0[44]; /* 0x114 - 0x13F: Reserved */
71 __R uint8_t RESERVED1[108]; /* 0x154 - 0x1BF: Reserved */
82 __R uint8_t RESERVED2[4]; /* 0x1E8 - 0x1EB: Reserved */
83 __R uint32_t BR_CUR_POS_TIME; /* 0x1EC: Monitor of the output timestamp */
84 __R uint32_t BR_CUR_POS; /* 0x1F0: Monitor of the output position */
85 __R uint32_t BR_CUR_REV; /* 0x1F4: Monitor of the output revolution */
86 __R uint32_t BR_CUR_SPEED; /* 0x1F8: Monitor of the output speed */
[all …]
A Dhpm_gpio_regs.h14 __R uint32_t VALUE; /* 0x0: GPIO input value */
15 __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */
17 __R uint8_t RESERVED0[16]; /* 0xF0 - 0xFF: Reserved */
24 __R uint8_t RESERVED1[16]; /* 0x1F0 - 0x1FF: Reserved */
31 __R uint8_t RESERVED2[16]; /* 0x2F0 - 0x2FF: Reserved */
34 __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */
36 __R uint8_t RESERVED3[16]; /* 0x3F0 - 0x3FF: Reserved */
43 __R uint8_t RESERVED4[16]; /* 0x4F0 - 0x4FF: Reserved */
50 __R uint8_t RESERVED5[16]; /* 0x5F0 - 0x5FF: Reserved */
57 __R uint8_t RESERVED6[16]; /* 0x6F0 - 0x6FF: Reserved */
[all …]
A Dhpm_qeiv2_regs.h27 __R uint32_t PH; /* 0x34: Phase counter */
29 __R uint32_t TMR; /* 0x3C: Timer counter */
42 __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */
44 __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */
46 __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */
47 __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */
48 __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */
49 __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */
53 __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */
55 __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */
[all …]
A Dhpm_plic_sw_regs.h13 __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */
15 __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */
17 __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/
A Dhpm_plic_regs.h15 __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */
17 __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */
18 __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */
19 __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */
20 …__R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and ta…
21 __R uint32_t INFO; /* 0x1104: Version and the maximum priority */
22 __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */
25 __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */
27 __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */
31 __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */
[all …]
A Dhpm_plic_sw_regs.h13 __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */
15 __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */
17 __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */
/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/
A Dicc_regs.h70 #ifndef __R
71 #define __R volatile const macro
91 __R uint32_t rsv_0x8_0xff[62];
93 __R uint32_t rsv_0x104_0x6ff[383];
A Dbbsir_regs.h70 #ifndef __R
71 #define __R volatile const macro
90 __R uint32_t rsv_0x4;

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